195f673f62
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140 In eMMC HS400 switch sequence flow eMMC driver attempted to execute SEND_STATUS just after switching bus timing to high speed and before downgrading clock frequency to 52MHz. Since link was at that time in incorrect state SEND_STATUS was failing which made driver think switch to HS400 failed. This change makes driver always change clock frequency after switching bus timing and before executing SEND_STATUS. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Albecki Mateusz <mateusz.albecki@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>