Writes TianoCore debug logs into the CBMEM console ringbuffer, from where the user can retrieve them with the `cbmem` userspace utility. The intention is to aid in debugging non-fatal issues even in release builds, or simply make TianoCore's logs available to those interested. Consequently, MDEPKG_NDEBUG must be masked. As an in-memory debug logging library, ASSERTs must be non-fatal to be seen, so they neither dead-loop nor create a breakpoint. It is assumed that ASSERT() neither enforces fatal conditions nor security integrity, as release builds do not call DebugAssert() from the ASSERT macro. More detailed debug logs are produced with the DEBUG_CODE macro, but this guards other debug-related code throughout the codebase. To avoid changing behaviour on release builds, this is only set for debug builds. Tested on QEMU, dumping the appropriate memory region in the UEFI shell shows the TianoCore log. An improved revision of the debug library used in several coreboot-related EDK2 forks, including MrChromebox's. Previous revisions also tested on an Acer Aspire VN7-572G laptop. Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
		
			
				
	
	
		
			264 lines
		
	
	
		
			6.8 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			264 lines
		
	
	
		
			6.8 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/** @file
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  Coreboot PEI module include file.
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  Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
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  SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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/*
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 * This file is part of the libpayload project.
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 *
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 * Copyright (C) 2008 Advanced Micro Devices, Inc.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * 1. Redistributions of source code must retain the above copyright
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 *    notice, this list of conditions and the following disclaimer.
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 * 2. Redistributions in binary form must reproduce the above copyright
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 *    notice, this list of conditions and the following disclaimer in the
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 *    documentation and/or other materials provided with the distribution.
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 * 3. The name of the author may not be used to endorse or promote products
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 *    derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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 * SUCH DAMAGE.
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 */
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#ifndef _COREBOOT_PEI_H_INCLUDED_
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#define _COREBOOT_PEI_H_INCLUDED_
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#if defined (_MSC_VER)
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  #pragma warning( disable : 4200 )
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#endif
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#define DYN_CBMEM_ALIGN_SIZE  (4096)
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#define IMD_ENTRY_MAGIC    (~0xC0389481)
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#define CBMEM_ENTRY_MAGIC  (~0xC0389479)
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struct cbmem_entry {
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  UINT32    magic;
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  UINT32    start;
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  UINT32    size;
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  UINT32    id;
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};
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struct cbmem_root {
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  UINT32                max_entries;
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  UINT32                num_entries;
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  UINT32                locked;
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  UINT32                size;
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  struct cbmem_entry    entries[0];
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};
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struct imd_entry {
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  UINT32    magic;
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  UINT32    start_offset;
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  UINT32    size;
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  UINT32    id;
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};
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struct imd_root {
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  UINT32              max_entries;
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  UINT32              num_entries;
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  UINT32              flags;
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  UINT32              entry_align;
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  UINT32              max_offset;
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  struct imd_entry    entries[0];
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};
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struct cbuint64 {
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  UINT32    lo;
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  UINT32    hi;
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};
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#define CB_HEADER_SIGNATURE  0x4F49424C
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struct cb_header {
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  UINT32    signature;
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  UINT32    header_bytes;
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  UINT32    header_checksum;
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  UINT32    table_bytes;
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  UINT32    table_checksum;
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  UINT32    table_entries;
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};
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struct cb_record {
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  UINT32    tag;
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  UINT32    size;
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};
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#define CB_TAG_UNUSED  0x0000
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#define CB_TAG_MEMORY  0x0001
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struct cb_memory_range {
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  struct cbuint64    start;
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  struct cbuint64    size;
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  UINT32             type;
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};
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#define CB_MEM_RAM          1
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#define CB_MEM_RESERVED     2
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#define CB_MEM_ACPI         3
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#define CB_MEM_NVS          4
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#define CB_MEM_UNUSABLE     5
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#define CB_MEM_VENDOR_RSVD  6
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#define CB_MEM_TABLE        16
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struct cb_memory {
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  UINT32                    tag;
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  UINT32                    size;
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  struct cb_memory_range    map[0];
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};
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#define CB_TAG_MAINBOARD  0x0003
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struct cb_mainboard {
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  UINT32    tag;
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  UINT32    size;
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  UINT8     vendor_idx;
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  UINT8     part_number_idx;
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  UINT8     strings[0];
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};
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#define CB_TAG_VERSION         0x0004
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#define CB_TAG_EXTRA_VERSION   0x0005
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#define CB_TAG_BUILD           0x0006
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#define CB_TAG_COMPILE_TIME    0x0007
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#define CB_TAG_COMPILE_BY      0x0008
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#define CB_TAG_COMPILE_HOST    0x0009
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#define CB_TAG_COMPILE_DOMAIN  0x000a
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#define CB_TAG_COMPILER        0x000b
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#define CB_TAG_LINKER          0x000c
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#define CB_TAG_ASSEMBLER       0x000d
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struct cb_string {
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  UINT32    tag;
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  UINT32    size;
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  UINT8     string[0];
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};
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#define CB_TAG_SERIAL  0x000f
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struct cb_serial {
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  UINT32    tag;
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  UINT32    size;
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  #define CB_SERIAL_TYPE_IO_MAPPED      1
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  #define CB_SERIAL_TYPE_MEMORY_MAPPED  2
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  UINT32    type;
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  UINT32    baseaddr;
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  UINT32    baud;
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  UINT32    regwidth;
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  // Crystal or input frequency to the chip containing the UART.
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  // Provide the board specific details to allow the payload to
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  // initialize the chip containing the UART and make independent
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  // decisions as to which dividers to select and their values
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  // to eventually arrive at the desired console baud-rate.
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  UINT32    input_hertz;
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  // UART PCI address: bus, device, function
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  // 1 << 31 - Valid bit, PCI UART in use
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  // Bus << 20
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  // Device << 15
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  // Function << 12
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  UINT32    uart_pci_addr;
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};
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#define CB_TAG_CONSOLE  0x00010
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struct cb_console {
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  UINT32    tag;
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  UINT32    size;
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  UINT16    type;
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};
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#define CB_TAG_CONSOLE_SERIAL8250  0
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#define CB_TAG_CONSOLE_VGA         1 // OBSOLETE
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#define CB_TAG_CONSOLE_BTEXT       2 // OBSOLETE
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#define CB_TAG_CONSOLE_LOGBUF      3
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#define CB_TAG_CONSOLE_SROM        4// OBSOLETE
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#define CB_TAG_CONSOLE_EHCI        5
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#define CB_TAG_FORWARD  0x00011
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struct cb_forward {
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  UINT32    tag;
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  UINT32    size;
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  UINT64    forward;
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};
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struct cb_cbmem_ref {
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  UINT32    tag;
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  // Field contains size of this struct == 0x0010
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  UINT32    size;
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  UINT64    cbmem_addr;
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};
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#define CB_TAG_FRAMEBUFFER  0x0012
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struct cb_framebuffer {
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  UINT32    tag;
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  UINT32    size;
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  UINT64    physical_address;
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  UINT32    x_resolution;
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  UINT32    y_resolution;
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  UINT32    bytes_per_line;
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  UINT8     bits_per_pixel;
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  UINT8     red_mask_pos;
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  UINT8     red_mask_size;
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  UINT8     green_mask_pos;
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  UINT8     green_mask_size;
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  UINT8     blue_mask_pos;
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  UINT8     blue_mask_size;
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  UINT8     reserved_mask_pos;
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  UINT8     reserved_mask_size;
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};
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#define CB_TAG_VDAT  0x0015
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struct cb_vdat {
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  UINT32    tag;
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  UINT32    size; /* size of the entire entry */
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  UINT64    vdat_addr;
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  UINT32    vdat_size;
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};
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#define CB_TAG_TIMESTAMPS     0x0016
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#define CB_TAG_CBMEM_CONSOLE  0x0017
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struct cbmem_console {
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  UINT32    size;
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  UINT32    cursor;
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  UINT8     body[0];
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} __attribute__ ((packed));
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#define CB_TAG_MRC_CACHE  0x0018
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struct cb_cbmem_tab {
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  UINT32    tag;
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  UINT32    size;
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  UINT64    cbmem_tab;
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};
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/* Helpful macros */
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#define MEM_RANGE_COUNT(_rec) \
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  (((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0]))
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#define MEM_RANGE_PTR(_rec, _idx) \
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  (void *)(((UINT8 *) (_rec)) + sizeof(*(_rec)) \
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    + (sizeof((_rec)->map[0]) * (_idx)))
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typedef struct cb_memory CB_MEMORY;
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#endif // _COREBOOT_PEI_H_INCLUDED_
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