465663e9f1
ARM TZASC-380 IP provides a mechanism to split memory regions being protected via it into eight equal-sized sub-regions. A bit-setting allows the corresponding subregion to be disabled. Several NXP/FSL SoCs support the TZASC-380 IP block and allow the DDR connected via the TZASC to be partitioned into regions having different security settings and also allow subregions to be disabled. This patch enables this support and can be used for SoCs which support such a partition of DDR regions. Details of the 'subregion_disable' register can be viewed here: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0431c/CHDIGDCI.html Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Bhupesh Sharma <bhupesh.sharma@nxp.com> [bhupesh.linux@gmail.com : Added gmail ID as NXP one is no longer valid] Signed-off-by: Bhupesh Sharma <bhupesh.linux@gmail.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
114 lines
2.7 KiB
C
114 lines
2.7 KiB
C
/** @file
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*
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* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Library/BaseLib.h>
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#include <Library/IoLib.h>
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#include <Drivers/ArmTrustzone.h>
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#define TZPC_DECPROT0_STATUS_REG 0x800
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#define TZPC_DECPROT0_SET_REG 0x804
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#define TZPC_DECPROT0_CLEAR_REG 0x808
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#define TZASC_CONFIGURATION_REG 0x000
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#define TZASC_REGIONS_REG 0x100
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#define TZASC_REGION0_LOW_ADDRESS_REG 0x100
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#define TZASC_REGION0_HIGH_ADDRESS_REG 0x104
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#define TZASC_REGION0_ATTRIBUTES 0x108
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/**
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FIXME: Need documentation
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**/
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EFI_STATUS
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TZPCSetDecProtBits (
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IN UINTN TzpcBase,
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IN UINTN TzpcId,
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IN UINTN Bits
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)
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{
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if (TzpcId > TZPC_DECPROT_MAX) {
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return EFI_INVALID_PARAMETER;
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}
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MmioWrite32 ((UINTN)TzpcBase + TZPC_DECPROT0_SET_REG + (TzpcId * 0x0C), Bits);
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return EFI_SUCCESS;
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}
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/**
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FIXME: Need documentation
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**/
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EFI_STATUS
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TZPCClearDecProtBits (
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IN UINTN TzpcBase,
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IN UINTN TzpcId,
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IN UINTN Bits
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)
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{
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if (TzpcId> TZPC_DECPROT_MAX) {
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return EFI_INVALID_PARAMETER;
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}
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MmioWrite32 ((UINTN)TzpcBase + TZPC_DECPROT0_CLEAR_REG + (TzpcId * 0x0C), Bits);
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return EFI_SUCCESS;
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}
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/**
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FIXME: Need documentation
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**/
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UINT32
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TZASCGetNumRegions (
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IN UINTN TzascBase
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)
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{
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return (MmioRead32 ((UINTN)TzascBase + TZASC_CONFIGURATION_REG) & 0xF);
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}
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/**
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FIXME: Need documentation
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**/
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EFI_STATUS
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TZASCSetRegion (
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IN INTN TzascBase,
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IN UINTN RegionId,
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IN UINTN Enabled,
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IN UINTN LowAddress,
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IN UINTN HighAddress,
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IN UINTN Size,
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IN UINTN Security,
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IN UINTN SubregionDisableMask
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)
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{
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UINT32* Region;
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UINT32 RegionAttributes;
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if (RegionId > TZASCGetNumRegions(TzascBase)) {
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return EFI_INVALID_PARAMETER;
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}
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RegionAttributes = TZASC_REGION_ATTR_SECURITY(Security) |
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TZASC_REGION_ATTR_SUBREG_DISABLE(SubregionDisableMask) |
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TZASC_REGION_ATTR_SIZE(Size) |
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TZASC_REGION_ATTR_ENABLE(Enabled);
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Region = (UINT32*)((UINTN)TzascBase + TZASC_REGIONS_REG + (RegionId * 0x10));
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MmioWrite32((UINTN)(Region), TZASC_REGION_SETUP_LO_ADDR(LowAddress));
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MmioWrite32((UINTN)(Region+1), HighAddress);
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MmioWrite32((UINTN)(Region+2), RegionAttributes);
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return EFI_SUCCESS;
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}
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