3cbfba02fe
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
154 lines
4.3 KiB
C
154 lines
4.3 KiB
C
/** @file
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Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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SlotConfig.c
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Abstract:
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Sets platform/SKU specific expansion slot information.
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--*/
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#include "SlotConfig.h"
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//
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// Implementation
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//
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VOID
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InitializeSlotInfo (
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)
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{
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UINT16 BusSaveState;
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UINT16 Vendor;
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UINT8 CurrentBus;
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UINTN i;
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UINTN j;
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EFI_HANDLE Handle;
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EFI_STATUS Status;
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BOOLEAN RunNext;
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//
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// Loop through the slot table and see if any slots have cards in them
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//
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for (i = 0; i < mSlotBridgeTableSize; i++) {
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//
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// Initialize variable
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//
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RunNext = FALSE;
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//
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// Hide mini PCIe slots per SKU
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//
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for (j = 0; j < mSlotInformation.NumberOfEntries; j++) {
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if (mSlotInformation.SlotEntries[j].SmbiosSlotId == mSlotBridgeTable[i].SmbiosSlotId) {
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if ((mSlotInformation.SlotEntries[j].SmbiosSlotId == 0x02) &&
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(mBoardFeatures & B_BOARD_FEATURES_NO_MINIPCIE)
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) {
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mSlotInformation.SlotEntries[j].Disabled = TRUE;
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RunNext = TRUE;
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}
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break;
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}
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}
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if (RunNext) {
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//
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// Skip slot device detection since the slot is disabled.
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//
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continue;
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}
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//
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// Check to see if the bridge has a bus number and assign one if not
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//
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BusSaveState = MmPci16 (
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0,
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mSlotBridgeTable[i].Bus,
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mSlotBridgeTable[i].Dev,
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mSlotBridgeTable[i].Function,
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PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET
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);
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if (BusSaveState == 0) {
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//
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// Assign temp bus number
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//
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MmPci16 (
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0,
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mSlotBridgeTable[i].Bus,
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mSlotBridgeTable[i].Dev,
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mSlotBridgeTable[i].Function,
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PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET
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) = DEF_BUS_CONFIG;
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CurrentBus = DEF_BUS;
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} else if (BusSaveState == 0xFFFF) {
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//
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// Bridge is disabled so continue with next entry in the table
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//
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continue;
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} else {
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//
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// Use existing bus number
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//
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CurrentBus = (UINT8) BusSaveState & 0xFF;
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}
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//
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// Check to see if a device is behind the bridge
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//
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Vendor = MmPci16 (
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0,
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CurrentBus,
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mSlotBridgeTable[i].TargetDevice,
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0,
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0
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);
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if (Vendor != 0xFFFF) {
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//
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// Device found so make sure the slot is marked that way
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//
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for (j = 0; j < mSlotInformation.NumberOfEntries; j++) {
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if (mSlotInformation.SlotEntries[j].SmbiosSlotId == mSlotBridgeTable[i].SmbiosSlotId) {
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mSlotInformation.SlotEntries[j].InUse = TRUE;
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break;
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}
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}
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}
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//
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// Restore previous bus information
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//
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if (BusSaveState == 0) {
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MmPci16 (
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0,
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mSlotBridgeTable[i].Bus,
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mSlotBridgeTable[i].Dev,
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mSlotBridgeTable[i].Function,
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PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET
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) = 0;
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}
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}
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Handle = NULL;
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Status = gBS->InstallProtocolInterface (
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&Handle,
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&gEfiSmbiosSlotPopulationGuid,
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EFI_NATIVE_INTERFACE,
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&mSlotInformation
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);
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ASSERT_EFI_ERROR(Status);
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}
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