3cbfba02fe
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
151 lines
5.5 KiB
C
151 lines
5.5 KiB
C
/*++
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Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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PlatformMemoryRange.h
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Abstract:
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Platform Memory Range PPI as defined in EFI 2.0
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PPI for reserving special purpose memory ranges.
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--*/
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//
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//
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#ifndef _PEI_PLATFORM_MEMORY_RANGE_H_
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#define _PEI_PLATFORM_MEMORY_RANGE_H_
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#define PEI_PLATFORM_MEMORY_RANGE_PPI_GUID \
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{ \
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0x30eb2979, 0xb0f7, 0x4d60, 0xb2, 0xdc, 0x1a, 0x2c, 0x96, 0xce, 0xb1, 0xf4 \
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}
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typedef struct _PEI_PLATFORM_MEMORY_RANGE_PPI PEI_PLATFORM_MEMORY_RANGE_PPI ;
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#define PEI_MEMORY_RANGE_OPTION_ROM UINT32
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#define PEI_MR_OPTION_ROM_ALL 0xFFFFFFFF
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#define PEI_MR_OPTION_ROM_NONE 0x00000000
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#define PEI_MR_OPTION_ROM_C0000_16K 0x00000001
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#define PEI_MR_OPTION_ROM_C4000_16K 0x00000002
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#define PEI_MR_OPTION_ROM_C8000_16K 0x00000004
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#define PEI_MR_OPTION_ROM_CC000_16K 0x00000008
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#define PEI_MR_OPTION_ROM_D0000_16K 0x00000010
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#define PEI_MR_OPTION_ROM_D4000_16K 0x00000020
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#define PEI_MR_OPTION_ROM_D8000_16K 0x00000040
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#define PEI_MR_OPTION_ROM_DC000_16K 0x00000080
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#define PEI_MR_OPTION_ROM_E0000_16K 0x00000100
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#define PEI_MR_OPTION_ROM_E4000_16K 0x00000200
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#define PEI_MR_OPTION_ROM_E8000_16K 0x00000400
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#define PEI_MR_OPTION_ROM_EC000_16K 0x00000800
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#define PEI_MR_OPTION_ROM_F0000_16K 0x00001000
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#define PEI_MR_OPTION_ROM_F4000_16K 0x00002000
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#define PEI_MR_OPTION_ROM_F8000_16K 0x00004000
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#define PEI_MR_OPTION_ROM_FC000_16K 0x00008000
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//
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// SMRAM Memory Range
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//
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#define PEI_MEMORY_RANGE_SMRAM UINT32
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#define PEI_MR_SMRAM_ALL 0xFFFFFFFF
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#define PEI_MR_SMRAM_NONE 0x00000000
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#define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000
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#define PEI_MR_SMRAM_SEGTYPE_MASK 0x00FF0000
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#define PEI_MR_SMRAM_ABSEG_MASK 0x00010000
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#define PEI_MR_SMRAM_HSEG_MASK 0x00020000
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#define PEI_MR_SMRAM_TSEG_MASK 0x00040000
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//
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// If adding additional entries, SMRAM Size
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// is a multiple of 128KB.
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//
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#define PEI_MR_SMRAM_SIZE_MASK 0x0000FFFF
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#define PEI_MR_SMRAM_SIZE_128K_MASK 0x00000001
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#define PEI_MR_SMRAM_SIZE_256K_MASK 0x00000002
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#define PEI_MR_SMRAM_SIZE_512K_MASK 0x00000004
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#define PEI_MR_SMRAM_SIZE_1024K_MASK 0x00000008
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#define PEI_MR_SMRAM_SIZE_2048K_MASK 0x00000010
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#define PEI_MR_SMRAM_SIZE_4096K_MASK 0x00000020
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#define PEI_MR_SMRAM_SIZE_8192K_MASK 0x00000040
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#define PEI_MR_SMRAM_ABSEG_128K_NOCACHE 0x00010001
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#define PEI_MR_SMRAM_HSEG_128K_CACHE 0x80020001
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#define PEI_MR_SMRAM_HSEG_128K_NOCACHE 0x00020001
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#define PEI_MR_SMRAM_TSEG_128K_CACHE 0x80040001
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#define PEI_MR_SMRAM_TSEG_128K_NOCACHE 0x00040001
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#define PEI_MR_SMRAM_TSEG_256K_CACHE 0x80040002
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#define PEI_MR_SMRAM_TSEG_256K_NOCACHE 0x00040002
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#define PEI_MR_SMRAM_TSEG_512K_CACHE 0x80040004
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#define PEI_MR_SMRAM_TSEG_512K_NOCACHE 0x00040004
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#define PEI_MR_SMRAM_TSEG_1024K_CACHE 0x80040008
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#define PEI_MR_SMRAM_TSEG_1024K_NOCACHE 0x00040008
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//
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// Graphics Memory Range
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//
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#define PEI_MEMORY_RANGE_GRAPHICS_MEMORY UINT32
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#define PEI_MR_GRAPHICS_MEMORY_ALL 0xFFFFFFFF
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#define PEI_MR_GRAPHICS_MEMORY_NONE 0x00000000
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#define PEI_MR_GRAPHICS_MEMORY_CACHEABLE 0x80000000
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//
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// If adding additional entries, Graphics Memory Size
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// is a multiple of 512KB.
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//
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#define PEI_MR_GRAPHICS_MEMORY_SIZE_MASK 0x0000FFFF
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#define PEI_MR_GRAPHICS_MEMORY_512K_NOCACHE 0x00000001
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#define PEI_MR_GRAPHICS_MEMORY_512K_CACHE 0x80000001
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#define PEI_MR_GRAPHICS_MEMORY_1M_NOCACHE 0x00000002
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#define PEI_MR_GRAPHICS_MEMORY_1M_CACHE 0x80000002
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#define PEI_MR_GRAPHICS_MEMORY_4M_NOCACHE 0x00000008
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#define PEI_MR_GRAPHICS_MEMORY_4M_CACHE 0x80000008
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#define PEI_MR_GRAPHICS_MEMORY_8M_NOCACHE 0x00000010
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#define PEI_MR_GRAPHICS_MEMORY_8M_CACHE 0x80000010
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#define PEI_MR_GRAPHICS_MEMORY_16M_NOCACHE 0x00000020
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#define PEI_MR_GRAPHICS_MEMORY_16M_CACHE 0x80000020
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#define PEI_MR_GRAPHICS_MEMORY_32M_NOCACHE 0x00000040
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#define PEI_MR_GRAPHICS_MEMORY_32M_CACHE 0x80000040
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#define PEI_MR_GRAPHICS_MEMORY_48M_NOCACHE 0x00000060
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#define PEI_MR_GRAPHICS_MEMORY_48M_CACHE 0x80000060
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#define PEI_MR_GRAPHICS_MEMORY_64M_NOCACHE 0x00000080
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#define PEI_MR_GRAPHICS_MEMORY_64M_CACHE 0x80000080
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#define PEI_MR_GRAPHICS_MEMORY_128M_NOCACHE 0x00000100
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#define PEI_MR_GRAPHICS_MEMORY_128M_CACHE 0x80000100
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#define PEI_MR_GRAPHICS_MEMORY_256M_NOCACHE 0x00000200
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#define PEI_MR_GRAPHICS_MEMORY_256M_CACHE 0x80000200
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//
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// Pci Memory Hole
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//
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#define PEI_MEMORY_RANGE_PCI_MEMORY UINT32
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#define PEI_MR_PCI_MEMORY_SIZE_512M_MASK 0x00000001
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typedef
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EFI_STATUS
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(EFIAPI *PEI_CHOOSE_RANGES) (
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IN EFI_PEI_SERVICES **PeiServices,
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IN PEI_PLATFORM_MEMORY_RANGE_PPI * This,
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IN OUT PEI_MEMORY_RANGE_OPTION_ROM * OptionRomMask,
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IN OUT PEI_MEMORY_RANGE_SMRAM * SmramMask,
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IN OUT PEI_MEMORY_RANGE_GRAPHICS_MEMORY * GraphicsMemoryMask,
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IN OUT PEI_MEMORY_RANGE_PCI_MEMORY * PciMemoryMask
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);
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struct _PEI_PLATFORM_MEMORY_RANGE_PPI {
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PEI_CHOOSE_RANGES ChooseRanges;
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};
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extern EFI_GUID gPeiPlatformMemoryRangePpiGuid;
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#endif
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