3cbfba02fe
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
800 lines
25 KiB
Plaintext
800 lines
25 KiB
Plaintext
/*-----------------------------------------------------------------------------
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Intel Silvermont Processor Power Management BIOS Reference Code
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Copyright (c) 2006 - 2014, Intel Corporation
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Filename: CPUPM.ASL
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Revision: Refer to Readme
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Date: Refer to Readme
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-------------------------------------------------------------------------------
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This Processor Power Management BIOS Source Code is furnished under license
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and may only be used or copied in accordance with the terms of the license.
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The information in this document is furnished for informational use only, is
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subject to change without notice, and should not be construed as a commitment
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by Intel Corporation. Intel Corporation assumes no responsibility or liability
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for any errors or inaccuracies that may appear in this document or any
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software that may be provided in association with this document.
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Except as permitted by such license, no part of this document may be
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reproduced, stored in a retrieval system, or transmitted in any form or by
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any means without the express written consent of Intel Corporation.
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WARNING: You are authorized and licensed to install and use this BIOS code
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ONLY on an IST PC. This utility may damage any system that does not
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meet these requirements.
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An IST PC is a computer which
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(1) Is capable of seamlessly and automatically transitioning among
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multiple performance states (potentially operating at different
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efficiency ratings) based upon power source changes, END user
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preference, processor performance demand, and thermal conditions; and
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(2) Includes an Intel Pentium II processors, Intel Pentium III
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processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
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Processor-M, Intel Pentium M Processor, or any other future Intel
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processors that incorporates the capability to transition between
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different performance states by altering some, or any combination of,
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the following processor attributes: core voltage, core frequency, bus
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frequency, number of processor cores available, or any other attribute
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that changes the efficiency (instructions/unit time-power) at which the
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processor operates.
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-------------------------------------------------------------------------------
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NOTES:
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(1) <TODO> - Except for the SSDT package, the objects in this ASL code
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may be moved to the DSDT. It is kept separate in this reference package
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for ease of distribution only.
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------------------------------------------------------------------------------*/
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DefinitionBlock (
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"CPUPM.aml",
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"SSDT",
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0x01,
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"PmRef",
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"CpuPm",
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0x3000
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)
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{
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External(\_PR.CPU0, DeviceObj)
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External(\_PR.CPU1, DeviceObj)
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External(\_PR.CPU2, DeviceObj)
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External(\_PR.CPU3, DeviceObj)
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External(SMIF)
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Scope(\)
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{
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// Package of pointers to SSDT's
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//
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// First column is SSDT name, used for debug only.
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// (First column must be EXACTLY eight characters.)
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// Second column is physical address.
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// Third column is table length.
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//
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// IF modifying this file, see warnings listed in ppminit.asm.
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//
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Name(SSDT,Package()
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{
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"CPU0IST ", 0x80000000, 0x80000000,
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"APIST ", 0x80000000, 0x80000000,
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"CPU0CST ", 0x80000000, 0x80000000,
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"APCST ", 0x80000000, 0x80000000
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})
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//
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// Note: See PpmBiosInit in PPMINIT.ASM for a definition of
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// the PpmFlags mirrored in CFGD.
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//
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Name(CFGD, 0x80000000)
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Name(\PDC0,0x80000000) // CPU0 _PDC Flags.
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Name(\PDC1,0x80000000) // CPU1 _PDC Flags.
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Name(\PDC2,0x80000000) // CPU2 _PDC Flags.
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Name(\PDC3,0x80000000) // CPU3 _PDC Flags.
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Name(\SDTL,0x00) // Loaded SSDT Flags.
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}
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Scope(\_PR.CPU0)
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{
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//
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// Define handles for opregions (used by load.)
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//
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Name(HI0,0) // Handle to CPU0IST
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Name(HC0,0) // Handle to CPU0CST
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Method(_PDC,1)
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{
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//
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// Check and extract the _PDC information.
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//
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Store(CPDC(Arg0), Local0)
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//
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// Save the capability information and load tables as needed.
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//
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GCAP(Local0)
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//
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// Return status.
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//
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//Return (Local0)
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}
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Method(_OSC, 4)
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{
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//
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// Check and extract the _OSC information.
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//
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Store(COSC(Arg0, Arg1, Arg2, Arg3), Local0)
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//
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// Save the capability information and load tables as needed.
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//
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GCAP(Local0)
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//
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// Return status.
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//
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Return (Local0)
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}
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//
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// Implement a generic Method to check _PDC information which may be called
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// by any of the processor scopes. (The use of _PDC is deprecated in ACPI 3.
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// in favor of _OSC. However, for backwards compatibility, _PDC may be
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// implemented using _OSC as follows:)
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//
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Method(CPDC,1)
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{
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CreateDwordField (Arg0, 0, REVS)
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CreateDwordField (Arg0, 4, SIZE)
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//
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// Local0 = Number of bytes for Arg0
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//
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Store (SizeOf (Arg0), Local0)
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//
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// Local1 = Number of Capabilities bytes in Arg0
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//
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Store (Subtract (Local0, 8), Local1)
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//
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// TEMP = Temporary field holding Capability DWORDs
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//
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CreateField (Arg0, 64, Multiply (Local1, 8), TEMP)
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//
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// Create the Status (STAT) buffer with the first DWORD = 0
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// This is required as per ACPI 3.0 Spec which says the
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// first DWORD is used to return errors defined by _OSC.
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//
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Name (STS0, Buffer () {0x00, 0x00, 0x00, 0x00})
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//
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// Concatenate the _PDC capabilities bytes to the STS0 Buffer
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// and store them in a local variable for calling OSC
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//
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Concatenate (STS0, TEMP, Local2)
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Return(COSC (ToUUID("4077A616-290C-47BE-9EBD-D87058713953"), REVS, SIZE, Local2))
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}
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//
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// Implement a generic Method to check _OSC information which may be called
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// by any of the processor scopes.
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//
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Method(COSC, 4)
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{
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//
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// Point to Status DWORD in the Arg3 buffer (STATUS)
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//
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CreateDWordField(Arg3, 0, STS0)
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//
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// Point to Caps DWORDs of the Arg3 buffer (CAPABILITIES)
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//
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CreateDwordField(Arg3, 4, CAP0)
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//
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// _OSC needs to validate the UUID and Revision.
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//
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// IF Unrecognized UUID
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// Return Unrecognized UUID _OSC Failure
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// IF Unsupported Revision
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// Return Unsupported Revision _OSC Failure
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//
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// STS0[0] = Reserved
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// STS0[1] = _OSC Failure
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// STS0[2] = Unrecognized UUID
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// STS0[3] = Unsupported Revision
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// STS0[4] = Capabilities masked
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//
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// Note: The comparison method used is necessary due to
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// limitations of certain OSes which cannot perform direct
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// buffer comparisons.
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//
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// Create a set of "Input" UUID fields.
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//
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CreateDwordField(Arg0, 0x0, IID0)
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CreateDwordField(Arg0, 0x4, IID1)
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CreateDwordField(Arg0, 0x8, IID2)
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CreateDwordField(Arg0, 0xC, IID3)
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//
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// Create a set of "Expected" UUID fields.
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//
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Name(UID0, ToUUID("4077A616-290C-47BE-9EBD-D87058713953"))
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CreateDwordField(UID0, 0x0, EID0)
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CreateDwordField(UID0, 0x4, EID1)
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CreateDwordField(UID0, 0x8, EID2)
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CreateDwordField(UID0, 0xC, EID3)
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//
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// Verify the input UUID matches the expected UUID.
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//
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If(LNot(LAnd(LAnd(LEqual(IID0, EID0),LEqual(IID1, EID1)),LAnd(LEqual(IID2, EID2),LEqual(IID3, EID3)))))
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{
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//
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// Return Unrecognized UUID _OSC Failure
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//
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Store (0x6, STS0)
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Return (Arg3)
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}
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If(LNot(LEqual(Arg1,1)))
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{
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//
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// Return Unsupported Revision _OSC Failure
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//
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Store (0xA, STS0)
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Return (Arg3)
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}
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Return (Arg3)
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}
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//
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// Get the capability information and load appropriate tables as needed.
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//
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Method(GCAP, 1)
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{
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// Point to Status DWORD in the Arg0 buffer (STATUS)
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CreateDWordField(Arg0, 0, STS0)
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// Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
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CreateDwordField(Arg0, 4, CAP0)
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//
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// If the UUID was unrecognized or the _OSC revision was unsupported,
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// return without updating capabilities.
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//
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If(LOr(LEqual(STS0,0x6),LEqual(STS0,0xA)))
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{
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Return()
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}
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//
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// Check if this is a query (BIT0 of Status = 1).
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// If so, mask off the bits we support and return.
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//
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if (And(STS0, 1))
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{
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And(CAP0, 0xBFF, CAP0)
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Return()
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}
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//
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// Store result of PDC. (We clear out the MSB, which was just
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// used as a placeholder for the compiler; and then "OR" the
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// value in case we get multiple calls, each of which only
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// reports partial support.)
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//
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Or(And(PDC0, 0x7FFFFFFF), CAP0, PDC0)
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//
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// Check IF the IST SSDTs should be loaded.
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//
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// CFGD[0] = GV3 Capable/Enabled
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//
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If(And(CFGD,0x01))
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{
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//
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// Load the IST SSDTs if:
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// (1) CMP capable and enabled.
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// (2) Driver supports P-States in MP configurations
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// (3) Driver supports direct HW P-State control
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// (4) SSDT is not already loaded
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//
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// CFGD[24] = Two or more cores enabled
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// PDCx[3] = OS supports C1 and P-states in MP systems
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// PDCx[0] = OS supports direct access of the perf MSR
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// SDTL[0] = CPU0 IST SSDT Loaded
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//
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If(LAnd(LAnd(And(CFGD,0x01000000),LEqual(And(PDC0, 0x0009), 0x0009)),LNot(And(SDTL,0x01))))
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{
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//
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// Flag the IST SSDT as loaded for CPU0
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//
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Or(SDTL, 0x01, SDTL)
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OperationRegion(IST0,SystemMemory,DeRefOf(Index(SSDT,1)),DeRefOf(Index(SSDT,2)))
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Load(IST0, HI0) // Dynamically load the CPU0IST SSDT
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}
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}
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//
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// Check IF the CST SSDTs should be loaded.
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//
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// CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled
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//
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If(And(CFGD,0x82))
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{
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//
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// Load the CST SSDTs if:
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// (1) CMP capable/enabled
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// (2) Driver supports multi-processor configurations
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// (3) CPU0 CST ISDT is not already loaded
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//
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// CFGD[24] = Two or more cores enabled
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// PDCx[3] = OS supports C1 and P-states in MP systems
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// PDCx[4] = OS supports ind. C2/C3 in MP systems
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// SDTL[1] = CPU0 CST SSDT Loaded
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//
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If(LAnd(LAnd(And(CFGD,0x01000000),And(PDC0,0x0018)),LNot(And(SDTL,0x02))))
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{
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//
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// Flag the CST SSDT as loaded for CPU0
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//
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Or(SDTL, 0x02, SDTL)
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OperationRegion(CST0,SystemMemory,DeRefOf(Index(SSDT,7)),DeRefOf(Index(SSDT,8)))
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Load(CST0, HC0) // Dynamically load the CPU0CST SSDT
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}
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}
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Return ()
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}
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}
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Scope(\_PR.CPU1)
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{
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//
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// Define handles for opregions (used by load.)
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//
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Name(HI1,0) // Handle to APIST
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Name(HC1,0) // Handle to APCST
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Method(_PDC,1)
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{
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//
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// Refer to \_PR.CPU0._PDC for description.
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//
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Store(\_PR.CPU0.CPDC(Arg0), Local0)
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GCAP(Local0)
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//Return (Local0)
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}
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Method(_OSC, 4)
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{
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//
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// Refer to \_PR.CPU0._OSC for description.
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//
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Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)
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GCAP(Local0)
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Return (Local0)
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}
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//
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// Get the capability information and load appropriate tables as needed.
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//
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Method(GCAP, 1)
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{
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//
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// Point to Status DWORD in the Arg0 buffer (STATUS)
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//
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CreateDWordField(Arg0, 0, STS1)
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//
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// Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
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//
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CreateDwordField(Arg0, 4, CAP1)
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//
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// If the UUID was unrecognized or the _OSC revision was unsupported,
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// return without updating capabilities.
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//
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If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))
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{
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Return()
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}
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//
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// Check if this is a query (BIT0 of Status = 1).
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// If so, mask off the bits we support and return.
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//
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if (And(STS1, 1))
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{
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And(CAP1, 0xBFF, CAP1)
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Return()
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}
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//
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// Store result of PDC. (We clear out the MSB, which was just
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// used as a placeholder for the compiler; and then "OR" the
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// value in case we get multiple calls, each of which only
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// reports partial support.)
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//
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Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)
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//
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// Attempt to dynamically load the IST SSDTs if:
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// (1) Driver supports P-States in MP configurations
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// (2) Driver supports direct HW P-State control
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//
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// PDCx[3] = OS supports C1 and P-states in MP systems
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// PDCx[0] = OS supports direct access of the perf MSR
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//
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If(LEqual(And(PDC0, 0x0009), 0x0009))
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{
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APPT()
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}
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//
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// Load the CST SSDTs if:
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// (1) Driver supports multi-processor configurations
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//
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// PDCx[3] = OS supports C1 and P-states in MP systems
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// PDCx[4] = OS supports ind. C2/C3 in MP systems
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//
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If(And(PDC0,0x0018))
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{
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APCT()
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}
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Return()
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}
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//
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// Dynamically load the CST SSDTs if:
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// (1) C-States are enabled
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// (2) SSDT is not already loaded
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//
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// CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled
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// SDTL[5] = AP CST SSDT Loaded
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//
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Method(APCT,0)
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{
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If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))
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{
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//
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// Flag the CST SSDT as loaded for the AP's
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//
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Or(SDTL, 0x20, SDTL)
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//
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// Dynamically load the APCST SSDT
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//
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OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))
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Load(CST1, HC1)
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}
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}
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//
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// Dynamically load the IST SSDTs if:
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// (1) If GV3 capable and enabled
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// (2) SSDT is not already loaded
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//
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// CFGD[0] = GV3 Capable/Enabled
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// SDTL[4] = AP IST SSDT Loaded
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//
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Method(APPT,0)
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{
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If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))
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{
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//
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// Flag the IST SSDT as loaded for CPU0
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//
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Or(SDTL, 0x10, SDTL)
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OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))
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Load(IST1, HI1) // Dynamically load the CPU1IST SSDT
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}
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}
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} // End CPU1
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Scope(\_PR.CPU2)
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{
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//
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// Define handles for opregions (used by load.)
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//
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Name(HI1,0) // Handle to APIST
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Name(HC1,0) // Handle to APCST
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Method(_PDC,1)
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{
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//
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// Refer to \_PR.CPU0._PDC for description.
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//
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Store(\_PR.CPU0.CPDC(Arg0), Local0)
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GCAP(Local0)
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//Return (Local0)
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}
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|
|
Method(_OSC, 4)
|
|
{
|
|
//
|
|
// Refer to \_PR.CPU0._OSC for description.
|
|
//
|
|
Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)
|
|
GCAP(Local0)
|
|
Return (Local0)
|
|
}
|
|
|
|
//
|
|
// Get the capability information and load appropriate tables as needed.
|
|
//
|
|
Method(GCAP, 1)
|
|
{
|
|
//
|
|
// Point to Status DWORD in the Arg0 buffer (STATUS)
|
|
//
|
|
CreateDWordField(Arg0, 0, STS1)
|
|
//
|
|
// Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
|
|
//
|
|
CreateDwordField(Arg0, 4, CAP1)
|
|
//
|
|
// If the UUID was unrecognized or the _OSC revision was unsupported,
|
|
// return without updating capabilities.
|
|
//
|
|
If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))
|
|
{
|
|
Return()
|
|
}
|
|
|
|
//
|
|
// Check if this is a query (BIT0 of Status = 1).
|
|
// If so, mask off the bits we support and return.
|
|
//
|
|
if (And(STS1, 1))
|
|
{
|
|
And(CAP1, 0xBFF, CAP1)
|
|
Return()
|
|
}
|
|
|
|
//
|
|
// Store result of PDC. (We clear out the MSB, which was just
|
|
// used as a placeholder for the compiler; and then "OR" the
|
|
// value in case we get multiple calls, each of which only
|
|
// reports partial support.)
|
|
//
|
|
Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)
|
|
|
|
//
|
|
// Attempt to dynamically load the IST SSDTs if:
|
|
// (1) Driver supports P-States in MP configurations
|
|
// (2) Driver supports direct HW P-State control
|
|
//
|
|
// PDCx[3] = OS supports C1 and P-states in MP systems
|
|
// PDCx[0] = OS supports direct access of the perf MSR
|
|
//
|
|
If(LEqual(And(PDC0, 0x0009), 0x0009))
|
|
{
|
|
APPT()
|
|
}
|
|
|
|
//
|
|
// Load the CST SSDTs if:
|
|
// (1) Driver supports multi-processor configurations
|
|
//
|
|
// PDCx[3] = OS supports C1 and P-states in MP systems
|
|
// PDCx[4] = OS supports ind. C2/C3 in MP systems
|
|
//
|
|
If(And(PDC0,0x0018))
|
|
{
|
|
APCT()
|
|
}
|
|
|
|
Return()
|
|
}
|
|
|
|
//
|
|
// Dynamically load the CST SSDTs if:
|
|
// (1) C-States are enabled
|
|
// (2) SSDT is not already loaded
|
|
//
|
|
// CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled
|
|
// SDTL[5] = AP CST SSDT Loaded
|
|
//
|
|
Method(APCT,0)
|
|
{
|
|
If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))
|
|
{
|
|
//
|
|
// Flag the CST SSDT as loaded for the AP's
|
|
//
|
|
Or(SDTL, 0x20, SDTL)
|
|
//
|
|
// Dynamically load the APCST SSDT
|
|
//
|
|
OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))
|
|
Load(CST1, HC1)
|
|
}
|
|
}
|
|
|
|
//
|
|
// Dynamically load the IST SSDTs if:
|
|
// (1) If GV3 capable and enabled
|
|
// (2) SSDT is not already loaded
|
|
//
|
|
// CFGD[0] = GV3 Capable/Enabled
|
|
// SDTL[4] = AP IST SSDT Loaded
|
|
//
|
|
Method(APPT,0)
|
|
{
|
|
If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))
|
|
{
|
|
//
|
|
// Flag the IST SSDT as loaded for CPU0
|
|
//
|
|
Or(SDTL, 0x10, SDTL)
|
|
|
|
OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))
|
|
Load(IST1, HI1) // Dynamically load the CPU1IST SSDT
|
|
}
|
|
}
|
|
} // End CPU1
|
|
|
|
Scope(\_PR.CPU3)
|
|
{
|
|
//
|
|
// Define handles for opregions (used by load.)
|
|
//
|
|
Name(HI1,0) // Handle to APIST
|
|
Name(HC1,0) // Handle to APCST
|
|
|
|
Method(_PDC,1)
|
|
{
|
|
//
|
|
// Refer to \_PR.CPU0._PDC for description.
|
|
//
|
|
Store(\_PR.CPU0.CPDC(Arg0), Local0)
|
|
GCAP(Local0)
|
|
//Return (Local0)
|
|
}
|
|
|
|
Method(_OSC, 4)
|
|
{
|
|
//
|
|
// Refer to \_PR.CPU0._OSC for description.
|
|
//
|
|
Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)
|
|
GCAP(Local0)
|
|
Return (Local0)
|
|
}
|
|
|
|
//
|
|
// Get the capability information and load appropriate tables as needed.
|
|
//
|
|
Method(GCAP, 1)
|
|
{
|
|
//
|
|
// Point to Status DWORD in the Arg0 buffer (STATUS)
|
|
//
|
|
CreateDWordField(Arg0, 0, STS1)
|
|
//
|
|
// Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
|
|
//
|
|
CreateDwordField(Arg0, 4, CAP1)
|
|
//
|
|
// If the UUID was unrecognized or the _OSC revision was unsupported,
|
|
// return without updating capabilities.
|
|
//
|
|
If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))
|
|
{
|
|
Return()
|
|
}
|
|
|
|
//
|
|
// Check if this is a query (BIT0 of Status = 1).
|
|
// If so, mask off the bits we support and return.
|
|
//
|
|
if (And(STS1, 1))
|
|
{
|
|
And(CAP1, 0xBFF, CAP1)
|
|
Return()
|
|
}
|
|
|
|
//
|
|
// Store result of PDC. (We clear out the MSB, which was just
|
|
// used as a placeholder for the compiler; and then "OR" the
|
|
// value in case we get multiple calls, each of which only
|
|
// reports partial support.)
|
|
//
|
|
Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)
|
|
|
|
//
|
|
// Attempt to dynamically load the IST SSDTs if:
|
|
// (1) Driver supports P-States in MP configurations
|
|
// (2) Driver supports direct HW P-State control
|
|
//
|
|
// PDCx[3] = OS supports C1 and P-states in MP systems
|
|
// PDCx[0] = OS supports direct access of the perf MSR
|
|
//
|
|
If(LEqual(And(PDC0, 0x0009), 0x0009))
|
|
{
|
|
APPT()
|
|
}
|
|
|
|
//
|
|
// Load the CST SSDTs if:
|
|
// (1) Driver supports multi-processor configurations
|
|
//
|
|
// PDCx[3] = OS supports C1 and P-states in MP systems
|
|
// PDCx[4] = OS supports ind. C2/C3 in MP systems
|
|
//
|
|
If(And(PDC0,0x0018))
|
|
{
|
|
APCT()
|
|
}
|
|
|
|
Return()
|
|
}
|
|
|
|
//
|
|
// Dynamically load the CST SSDTs if:
|
|
// (1) C-States are enabled
|
|
// (2) SSDT is not already loaded
|
|
//
|
|
// CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled
|
|
// SDTL[5] = AP CST SSDT Loaded
|
|
//
|
|
Method(APCT,0)
|
|
{
|
|
If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))
|
|
{
|
|
//
|
|
// Flag the CST SSDT as loaded for the AP's
|
|
//
|
|
Or(SDTL, 0x20, SDTL)
|
|
//
|
|
// Dynamically load the APCST SSDT
|
|
//
|
|
OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))
|
|
Load(CST1, HC1)
|
|
}
|
|
}
|
|
|
|
//
|
|
// Dynamically load the IST SSDTs if:
|
|
// (1) If GV3 capable and enabled
|
|
// (2) SSDT is not already loaded
|
|
//
|
|
// CFGD[0] = GV3 Capable/Enabled
|
|
// SDTL[4] = AP IST SSDT Loaded
|
|
//
|
|
Method(APPT,0)
|
|
{
|
|
If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))
|
|
{
|
|
//
|
|
// Flag the IST SSDT as loaded for CPU0
|
|
//
|
|
Or(SDTL, 0x10, SDTL)
|
|
|
|
OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))
|
|
Load(IST1, HI1) // Dynamically load the CPU1IST SSDT
|
|
}
|
|
}
|
|
} // End CPU3
|
|
} // End of Definition Block
|
|
|
|
|
|
|