b303605e1b
Changes for V4 ============== 1) Move delete of QuarkSocPkg\QuarkNorthCluster\Binary\QuarkMicrocode from QuarkPlatformPkg commit to QuarkSocPkg commit 2) Fix incorrect license header in PlatformSecLibModStrs.uni Changes for V3 ============== 1) Set PcdResetOnMemoryTypeInformationChange FALSE in QuarkMin.dsc This is required because QuarkMin.dsc uses the emulated variable driver that does not preserve any non-volatile UEFI variables across reset. If the condition is met where the memory type information variable needs to be updated, then the system will reset every time the UEFI Shell is run. By setting this PCD to FALSE, then reset action is disabled. 2) Move one binary file to QuarkSocBinPkg 3) Change RMU.bin FILE statements to INF statement in DSC FD region to be compatible with PACKAGES_PATH search for QuarkSocBinPkg Changes for V2 ============== 1) Use new generic PCI serial driver PciSioSerialDxe in MdeModulePkg 2) Configure PcdPciSerialParameters for PCI serial driver for Quark 3) Use new MtrrLib API to reduce time to set MTRRs for all DRAM 4) Convert all UNI files to utf-8 5) Replace tabs with spaces and remove trailing spaces 6) Add License.txt Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Acked-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19287 6f19259b-4bc3-4df7-8a09-765794883524
132 lines
3.7 KiB
C
132 lines
3.7 KiB
C
/** @file
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System On Chip Unit (SOCUnit) routines.
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Copyright (c) 2013-2015 Intel Corporation.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "CommonHeader.h"
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/** Early initialisation of the SOC Unit
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@retval EFI_SUCCESS Operation success.
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**/
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EFI_STATUS
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EFIAPI
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SocUnitEarlyInitialisation (
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VOID
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)
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{
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UINT32 NewValue;
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//
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// Set the mixer load resistance
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//
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NewValue = QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0);
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NewValue &= OCFGPIMIXLOAD_1_0_MASK;
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QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0, NewValue);
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NewValue = QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1);
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NewValue &= OCFGPIMIXLOAD_1_0_MASK;
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QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1, NewValue);
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return EFI_SUCCESS;
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}
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/** Tasks to release PCI controller from reset pre wait for PLL Lock.
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@retval EFI_SUCCESS Operation success.
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**/
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EFI_STATUS
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EFIAPI
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SocUnitReleasePcieControllerPreWaitPllLock (
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IN CONST EFI_PLATFORM_TYPE PlatformType
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)
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{
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UINT32 NewValue;
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//
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// Assert PERST# and validate time assertion time.
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//
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PlatformPERSTAssert (PlatformType);
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ASSERT (PCIEXP_PERST_MIN_ASSERT_US <= (PCIEXP_DELAY_US_POST_CMNRESET_RESET + PCIEXP_DELAY_US_WAIT_PLL_LOCK + PCIEXP_DELAY_US_POST_SBI_RESET));
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//
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// PHY Common lane reset.
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//
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NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);
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NewValue |= SOCCLKEN_CONFIG_PHY_I_CMNRESET_L;
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QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);
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//
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// Wait post common lane reset.
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//
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MicroSecondDelay (PCIEXP_DELAY_US_POST_CMNRESET_RESET);
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//
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// PHY Sideband interface reset.
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// Controller main reset
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//
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NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);
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NewValue |= (SOCCLKEN_CONFIG_SBI_RST_100_CORE_B | SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L);
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QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);
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return EFI_SUCCESS;
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}
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/** Tasks to release PCI controller from reset after PLL has locked
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@retval EFI_SUCCESS Operation success.
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**/
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EFI_STATUS
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EFIAPI
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SocUnitReleasePcieControllerPostPllLock (
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IN CONST EFI_PLATFORM_TYPE PlatformType
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)
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{
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UINT32 NewValue;
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//
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// Controller sideband interface reset.
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//
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NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);
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NewValue |= SOCCLKEN_CONFIG_SBI_BB_RST_B;
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QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);
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//
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// Wait post sideband interface reset.
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//
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MicroSecondDelay (PCIEXP_DELAY_US_POST_SBI_RESET);
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//
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// Deassert PERST#.
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//
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PlatformPERSTDeAssert (PlatformType);
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//
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// Wait post de assert PERST#.
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//
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MicroSecondDelay (PCIEXP_DELAY_US_POST_PERST_DEASSERT);
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//
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// Controller primary interface reset.
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//
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NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);
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NewValue |= SOCCLKEN_CONFIG_BB_RST_B;
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QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);
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return EFI_SUCCESS;
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}
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