9344f09215
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
91 lines
2.5 KiB
NASM
91 lines
2.5 KiB
NASM
;------------------------------------------------------------------------------
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;
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; Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
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;
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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EXPORT InternalMemZeroMem
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EXPORT InternalMemSetMem
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EXPORT InternalMemSetMem16
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EXPORT InternalMemSetMem32
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EXPORT InternalMemSetMem64
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AREA SetMem, CODE, READONLY, CODEALIGN, ALIGN=5
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THUMB
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InternalMemSetMem16
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uxth r2, r2
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lsl r1, r1, #1
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orr r2, r2, r2, lsl #16
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b B0
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InternalMemSetMem32
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lsl r1, r1, #2
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b B0
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InternalMemSetMem64
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lsl r1, r1, #3
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b B1
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ALIGN 32
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InternalMemSetMem
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uxtb r2, r2
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orr r2, r2, r2, lsl #8
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orr r2, r2, r2, lsl #16
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b B0
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InternalMemZeroMem
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movs r2, #0
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B0
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mov r3, r2
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B1
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push {r4, lr}
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cmp r1, #16 ; fewer than 16 bytes of input?
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add r1, r1, r0 ; r1 := dst + length
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add lr, r0, #16
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blt L2
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bic lr, lr, #15 ; align output pointer
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str r2, [r0] ; potentially unaligned store of 4 bytes
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str r3, [r0, #4] ; potentially unaligned store of 4 bytes
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str r2, [r0, #8] ; potentially unaligned store of 4 bytes
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str r3, [r0, #12] ; potentially unaligned store of 4 bytes
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beq L1
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L0
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add lr, lr, #16 ; advance the output pointer by 16 bytes
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subs r4, r1, lr ; past the output?
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blt L3 ; break out of the loop
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strd r2, r3, [lr, #-16] ; aligned store of 16 bytes
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strd r2, r3, [lr, #-8]
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bne L0 ; goto beginning of loop
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L1
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pop {r4, pc}
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L2
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subs r4, r1, lr
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L3
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adds r4, r4, #16
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subs r1, r1, #8
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cmp r4, #4 ; between 4 and 15 bytes?
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blt L4
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cmp r4, #8 ; between 8 and 15 bytes?
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str r2, [lr, #-16] ; overlapping store of 4 + (4 + 4) + 4 bytes
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itt gt
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strgt r3, [lr, #-12]
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strgt r2, [r1]
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str r3, [r1, #4]
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pop {r4, pc}
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L4
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cmp r4, #2 ; 2 or 3 bytes?
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strb r2, [lr, #-16] ; store 1 byte
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it ge
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strhge r2, [r1, #6] ; store 2 bytes
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pop {r4, pc}
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END
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