cf1d454983
Add FSP2.0 support. This series of patch is to support FSP2.0 specification at https://firmware.intel.com/sites/default/files/FSP_EAS_v2.0_Draft%20External.pdf Some major updates include: 1) One FSP binary is separated to multiple components: FSP-T, FSP-M, FSP-S, and optional FSP-O. Each component has its own configuration data region. 2) All FSP-APIs use same UPD format - FSP_UPD_HEADER. 3) Add EnumInitPhaseEndOfFirmware notifyphase. 4) FSP1.1/FSP1.0 compatibility is NOT maintained. 5) We also add rename Fsp* to FspWrapper* in IntelFsp2WrapperPkg, to indicate that it is for FspWrapper only. IntelFspPkg and IntelFspWrapperPkg will be deprecated. The new Intel platform will follow FSP2.0 and use IntelFsp2Pkg and IntelFsp2WrapperPkg. The old platform can still use IntelFspPkg and IntelFspWrapperPkg for compatibility consideration. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Ravi P Rangarajan <ravi.p.rangarajan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Ravi P Rangarajan <ravi.p.rangarajan@intel.com>
141 lines
2.6 KiB
NASM
141 lines
2.6 KiB
NASM
;------------------------------------------------------------------------------
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;
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; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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; Module Name:
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;
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; PeiCoreEntry.asm
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;
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; Abstract:
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;
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; Find and call SecStartup
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;
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;------------------------------------------------------------------------------
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.686p
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.xmm
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.model flat, c
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.code
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EXTRN SecStartup:NEAR
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EXTRN PlatformInit:NEAR
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CallPeiCoreEntryPoint PROC PUBLIC
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;
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; Obtain the hob list pointer
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;
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mov eax, [esp+4]
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;
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; Obtain the stack information
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; ECX: start of range
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; EDX: end of range
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;
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mov ecx, [esp+8]
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mov edx, [esp+0Ch]
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;
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; Platform init
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;
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pushad
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push edx
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push ecx
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push eax
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call PlatformInit
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pop eax
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pop eax
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pop eax
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popad
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;
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; Set stack top pointer
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;
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mov esp, edx
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;
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; Push the hob list pointer
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;
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push eax
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;
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; Save the value
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; ECX: start of range
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; EDX: end of range
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;
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mov ebp, esp
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push ecx
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push edx
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;
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; Push processor count to stack first, then BIST status (AP then BSP)
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;
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mov eax, 1
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cpuid
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shr ebx, 16
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and ebx, 0000000FFh
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cmp bl, 1
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jae PushProcessorCount
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;
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; Some processors report 0 logical processors. Effectively 0 = 1.
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; So we fix up the processor count
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;
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inc ebx
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PushProcessorCount:
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push ebx
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;
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; We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST
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; for all processor threads
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;
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xor ecx, ecx
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mov cl, bl
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PushBist:
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movd eax, mm0
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push eax
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loop PushBist
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; Save Time-Stamp Counter
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movd eax, mm5
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push eax
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movd eax, mm6
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push eax
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;
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; Pass entry point of the PEI core
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;
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mov edi, 0FFFFFFE0h
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push DWORD PTR ds:[edi]
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;
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; Pass BFV into the PEI Core
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;
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mov edi, 0FFFFFFFCh
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push DWORD PTR ds:[edi]
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;
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; Pass stack size into the PEI Core
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;
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mov ecx, [ebp - 4]
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mov edx, [ebp - 8]
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push ecx ; RamBase
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sub edx, ecx
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push edx ; RamSize
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;
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; Pass Control into the PEI Core
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;
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call SecStartup
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CallPeiCoreEntryPoint ENDP
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END
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