dcdfb2f083
Implement all of the FVB protocol functions on top of the SmmStore as a library. The library consumes the introduced gEfiSmmStoreInfoHobGuid. The SMI handler uses a fixed communication buffer in reserved DRAM. To initiate a transaction you must write to the I/O APM_CNT port. Tests on Intel(R) Xeon(R) E-2288G CPU @ 3.70G showed that the SMI isn't triggered with a probability of 1:40 of all cases when called in a tight loop. The CPU continues running and the SMI is triggeres asynchronously a few clock cycles later. coreboot only handels synchronous APM request and does nothing on asynchronous APM triggers. As there's no livesign from SMM it's impossible to tell if the handler has run. Just wait a bit and try again to trigger a synchronous SMI. Tests confirmed that out of 5 million tries the SMI is now always handled. When a synchronous SMI happens with the correct write to the APM_CNT port, the ebx register is checked first that it doesn't point to SMRAM. If it doesn't it's used to read in the arguments that define a SmmStore transaction. The SMI handler will only operate on a predefined and memory mapped region in the boot media. Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: Id4182623e4198c6512d3fe6ec20adf6738586d9b
82 lines
1.8 KiB
C
82 lines
1.8 KiB
C
/** @file SmmStore.h
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Copyright (c) 2022, 9elements GmbH<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef COREBOOT_SMMSTORE_H_
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#define COREBOOT_SMMSTORE_H_
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#define SMMSTORE_RET_SUCCESS 0
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#define SMMSTORE_RET_FAILURE 1
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#define SMMSTORE_RET_UNSUPPORTED 2
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/* Version 2 only */
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#define SMMSTORE_CMD_INIT 4
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#define SMMSTORE_CMD_RAW_READ 5
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#define SMMSTORE_CMD_RAW_WRITE 6
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#define SMMSTORE_CMD_RAW_CLEAR 7
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/*
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* This allows the payload to store raw data in the flash regions.
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* This can be used by a FaultTolerantWrite implementation, that uses at least
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* two regions in an A/B update scheme.
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*/
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#pragma pack(1)
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/*
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* Reads a chunk of raw data with size BufSize from the block specified by
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* block_id starting at BufOffset.
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* The read data is placed in buf.
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*
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* block_id must be less than num_blocks
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* BufOffset + BufSize must be less than block_size
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*/
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typedef struct {
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UINT32 BufSize;
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UINT32 BufOffset;
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UINT32 BlockId;
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} SMM_STORE_PARAMS_WRITE;
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/*
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* Writes a chunk of raw data with size BufSize to the block specified by
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* block_id starting at BufOffset.
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*
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* block_id must be less than num_blocks
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* BufOffset + BufSize must be less than block_size
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*/
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typedef struct {
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UINT32 BufSize;
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UINT32 BufOffset;
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UINT32 BlockId;
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} SMM_STORE_PARAMS_READ;
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/*
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* Erases the specified block.
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*
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* block_id must be less than num_blocks
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*/
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typedef struct {
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UINT32 BlockId;
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} SMM_STORE_PARAMS_CLEAR;
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typedef union {
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SMM_STORE_PARAMS_WRITE Write;
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SMM_STORE_PARAMS_READ Read;
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SMM_STORE_PARAMS_CLEAR Clear;
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} SMM_STORE_COM_BUF;
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#pragma pack(0)
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UINTN
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EFIAPI
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TriggerSmi (
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IN UINTN Cmd,
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IN UINTN Arg,
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IN UINTN Retry
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);
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#endif // COREBOOT_SMMSTORE_H_
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