8a1f540596
Now that we have a sane API to set and clear memory permissions that works the same on ARM and AArch64, we no longer have a need for the individual set/clear no-access/read-only/no-exec helpers so let's drop them. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
363 lines
11 KiB
C
363 lines
11 KiB
C
/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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Copyright (c) 2011, ARM Limited. All rights reserved.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "CpuDxe.h"
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#include <Guid/IdleLoopEvent.h>
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#include <Library/MemoryAllocationLib.h>
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BOOLEAN mIsFlushingGCD;
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/**
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This function flushes the range of addresses from Start to Start+Length
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from the processor's data cache. If Start is not aligned to a cache line
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boundary, then the bytes before Start to the preceding cache line boundary
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are also flushed. If Start+Length is not aligned to a cache line boundary,
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then the bytes past Start+Length to the end of the next cache line boundary
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are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be
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supported. If the data cache is fully coherent with all DMA operations, then
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this function can just return EFI_SUCCESS. If the processor does not support
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flushing a range of the data cache, then the entire data cache can be flushed.
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@param This The EFI_CPU_ARCH_PROTOCOL instance.
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@param Start The beginning physical address to flush from the processor's data
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cache.
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@param Length The number of bytes to flush from the processor's data cache. This
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function may flush more bytes than Length specifies depending upon
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the granularity of the flush operation that the processor supports.
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@param FlushType Specifies the type of flush operation to perform.
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@retval EFI_SUCCESS The address range from Start to Start+Length was flushed from
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the processor's data cache.
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@retval EFI_UNSUPPORTED The processor does not support the cache flush type specified
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by FlushType.
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@retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed
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from the processor's data cache.
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**/
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EFI_STATUS
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EFIAPI
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CpuFlushCpuDataCache (
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IN EFI_CPU_ARCH_PROTOCOL *This,
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IN EFI_PHYSICAL_ADDRESS Start,
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IN UINT64 Length,
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IN EFI_CPU_FLUSH_TYPE FlushType
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)
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{
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switch (FlushType) {
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case EfiCpuFlushTypeWriteBack:
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WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
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break;
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case EfiCpuFlushTypeInvalidate:
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InvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
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break;
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case EfiCpuFlushTypeWriteBackInvalidate:
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WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
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break;
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default:
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return EFI_INVALID_PARAMETER;
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}
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return EFI_SUCCESS;
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}
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/**
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This function enables interrupt processing by the processor.
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@param This The EFI_CPU_ARCH_PROTOCOL instance.
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@retval EFI_SUCCESS Interrupts are enabled on the processor.
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@retval EFI_DEVICE_ERROR Interrupts could not be enabled on the processor.
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**/
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EFI_STATUS
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EFIAPI
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CpuEnableInterrupt (
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IN EFI_CPU_ARCH_PROTOCOL *This
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)
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{
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ArmEnableInterrupts ();
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return EFI_SUCCESS;
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}
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/**
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This function disables interrupt processing by the processor.
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@param This The EFI_CPU_ARCH_PROTOCOL instance.
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@retval EFI_SUCCESS Interrupts are disabled on the processor.
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@retval EFI_DEVICE_ERROR Interrupts could not be disabled on the processor.
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**/
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EFI_STATUS
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EFIAPI
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CpuDisableInterrupt (
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IN EFI_CPU_ARCH_PROTOCOL *This
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)
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{
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ArmDisableInterrupts ();
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return EFI_SUCCESS;
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}
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/**
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This function retrieves the processor's current interrupt state a returns it in
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State. If interrupts are currently enabled, then TRUE is returned. If interrupts
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are currently disabled, then FALSE is returned.
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@param This The EFI_CPU_ARCH_PROTOCOL instance.
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@param State A pointer to the processor's current interrupt state. Set to TRUE if
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interrupts are enabled and FALSE if interrupts are disabled.
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@retval EFI_SUCCESS The processor's current interrupt state was returned in State.
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@retval EFI_INVALID_PARAMETER State is NULL.
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**/
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EFI_STATUS
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EFIAPI
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CpuGetInterruptState (
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IN EFI_CPU_ARCH_PROTOCOL *This,
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OUT BOOLEAN *State
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)
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{
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if (State == NULL) {
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return EFI_INVALID_PARAMETER;
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}
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*State = ArmGetInterruptState ();
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return EFI_SUCCESS;
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}
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/**
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This function generates an INIT on the processor. If this function succeeds, then the
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processor will be reset, and control will not be returned to the caller. If InitType is
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not supported by this processor, or the processor cannot programmatically generate an
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INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error
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occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.
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@param This The EFI_CPU_ARCH_PROTOCOL instance.
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@param InitType The type of processor INIT to perform.
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@retval EFI_SUCCESS The processor INIT was performed. This return code should never be seen.
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@retval EFI_UNSUPPORTED The processor INIT operation specified by InitType is not supported
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by this processor.
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@retval EFI_DEVICE_ERROR The processor INIT failed.
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**/
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EFI_STATUS
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EFIAPI
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CpuInit (
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IN EFI_CPU_ARCH_PROTOCOL *This,
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IN EFI_CPU_INIT_TYPE InitType
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)
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{
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return EFI_UNSUPPORTED;
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}
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EFI_STATUS
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EFIAPI
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CpuRegisterInterruptHandler (
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IN EFI_CPU_ARCH_PROTOCOL *This,
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IN EFI_EXCEPTION_TYPE InterruptType,
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IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
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)
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{
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return RegisterInterruptHandler (InterruptType, InterruptHandler);
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}
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EFI_STATUS
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EFIAPI
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CpuGetTimerValue (
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IN EFI_CPU_ARCH_PROTOCOL *This,
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IN UINT32 TimerIndex,
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OUT UINT64 *TimerValue,
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OUT UINT64 *TimerPeriod OPTIONAL
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)
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{
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return EFI_UNSUPPORTED;
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}
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/**
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Callback function for idle events.
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@param Event Event whose notification function is being invoked.
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@param Context The pointer to the notification function's context,
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which is implementation-dependent.
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**/
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VOID
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EFIAPI
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IdleLoopEventCallback (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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CpuSleep ();
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}
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//
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// Globals used to initialize the protocol
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//
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EFI_HANDLE mCpuHandle = NULL;
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EFI_CPU_ARCH_PROTOCOL mCpu = {
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CpuFlushCpuDataCache,
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CpuEnableInterrupt,
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CpuDisableInterrupt,
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CpuGetInterruptState,
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CpuInit,
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CpuRegisterInterruptHandler,
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CpuGetTimerValue,
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CpuSetMemoryAttributes,
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0, // NumberOfTimers
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2048, // DmaBufferAlignment
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};
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STATIC
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VOID
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InitializeDma (
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IN OUT EFI_CPU_ARCH_PROTOCOL *CpuArchProtocol
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)
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{
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CpuArchProtocol->DmaBufferAlignment = ArmCacheWritebackGranule ();
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}
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/**
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Map all EfiConventionalMemory regions in the memory map with NX
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attributes so that allocating or freeing EfiBootServicesData regions
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does not result in changes to memory permission attributes.
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**/
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STATIC
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VOID
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RemapUnusedMemoryNx (
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VOID
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)
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{
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UINT64 TestBit;
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UINTN MemoryMapSize;
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UINTN MapKey;
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UINTN DescriptorSize;
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UINT32 DescriptorVersion;
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EFI_MEMORY_DESCRIPTOR *MemoryMap;
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EFI_MEMORY_DESCRIPTOR *MemoryMapEntry;
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EFI_MEMORY_DESCRIPTOR *MemoryMapEnd;
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EFI_STATUS Status;
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TestBit = LShiftU64 (1, EfiBootServicesData);
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if ((PcdGet64 (PcdDxeNxMemoryProtectionPolicy) & TestBit) == 0) {
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return;
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}
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MemoryMapSize = 0;
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MemoryMap = NULL;
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Status = gBS->GetMemoryMap (
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&MemoryMapSize,
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MemoryMap,
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&MapKey,
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&DescriptorSize,
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&DescriptorVersion
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);
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ASSERT (Status == EFI_BUFFER_TOO_SMALL);
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do {
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MemoryMap = (EFI_MEMORY_DESCRIPTOR *)AllocatePool (MemoryMapSize);
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ASSERT (MemoryMap != NULL);
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Status = gBS->GetMemoryMap (
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&MemoryMapSize,
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MemoryMap,
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&MapKey,
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&DescriptorSize,
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&DescriptorVersion
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);
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if (EFI_ERROR (Status)) {
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FreePool (MemoryMap);
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}
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} while (Status == EFI_BUFFER_TOO_SMALL);
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ASSERT_EFI_ERROR (Status);
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MemoryMapEntry = MemoryMap;
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MemoryMapEnd = (EFI_MEMORY_DESCRIPTOR *)((UINT8 *)MemoryMap + MemoryMapSize);
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while ((UINTN)MemoryMapEntry < (UINTN)MemoryMapEnd) {
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if (MemoryMapEntry->Type == EfiConventionalMemory) {
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ArmSetMemoryAttributes (
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MemoryMapEntry->PhysicalStart,
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EFI_PAGES_TO_SIZE (MemoryMapEntry->NumberOfPages),
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EFI_MEMORY_XP,
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EFI_MEMORY_XP
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);
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}
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MemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize);
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}
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}
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EFI_STATUS
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CpuDxeInitialize (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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EFI_EVENT IdleLoopEvent;
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InitializeExceptions (&mCpu);
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InitializeDma (&mCpu);
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//
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// Once we install the CPU arch protocol, the DXE core's memory
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// protection routines will invoke them to manage the permissions of page
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// allocations as they are created. Given that this includes pages
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// allocated for page tables by this driver, we must ensure that unused
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// memory is mapped with the same permissions as boot services data
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// regions. Otherwise, we may end up with unbounded recursion, due to the
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// fact that updating permissions on a newly allocated page table may trigger
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// a block entry split, which triggers a page table allocation, etc etc
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//
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if (FeaturePcdGet (PcdRemapUnusedMemoryNx)) {
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RemapUnusedMemoryNx ();
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}
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Status = gBS->InstallMultipleProtocolInterfaces (
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&mCpuHandle,
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&gEfiCpuArchProtocolGuid,
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&mCpu,
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&gEfiMemoryAttributeProtocolGuid,
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&mMemoryAttribute,
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NULL
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);
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//
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// Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()
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// and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go
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// after the protocol is installed
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//
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mIsFlushingGCD = TRUE;
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SyncCacheConfig (&mCpu);
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mIsFlushingGCD = FALSE;
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//
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// Setup a callback for idle events
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//
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Status = gBS->CreateEventEx (
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EVT_NOTIFY_SIGNAL,
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TPL_NOTIFY,
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IdleLoopEventCallback,
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NULL,
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&gIdleLoopEventGuid,
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&IdleLoopEvent
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);
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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