47d20b54f9
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the ShellPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
39 lines
1.3 KiB
C
39 lines
1.3 KiB
C
/** @file
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Header file for PPTT parser
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Copyright (c) 2019, ARM Limited. All rights reserved.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Reference(s):
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- ARM Architecture Reference Manual ARMv8 (D.a)
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**/
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#ifndef PPTT_PARSER_H_
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#define PPTT_PARSER_H_
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#if defined (MDE_CPU_ARM) || defined (MDE_CPU_AARCH64)
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/// Cache parameters allowed by the architecture with
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/// ARMv8.3-CCIDX (Cache extended number of sets)
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/// Derived from CCSIDR_EL1 when ID_AA64MMFR2_EL1.CCIDX==0001
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#define PPTT_ARM_CCIDX_CACHE_NUMBER_OF_SETS_MAX (1 << 24)
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#define PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX (1 << 21)
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/// Cache parameters allowed by the architecture without
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/// ARMv8.3-CCIDX (Cache extended number of sets)
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/// Derived from CCSIDR_EL1 when ID_AA64MMFR2_EL1.CCIDX==0000
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#define PPTT_ARM_CACHE_NUMBER_OF_SETS_MAX (1 << 15)
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#define PPTT_ARM_CACHE_ASSOCIATIVITY_MAX (1 << 10)
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/// Common cache parameters
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/// Derived from CCSIDR_EL1
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/// The LineSize is represented by bits 2:0
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/// (Log2(Number of bytes in cache line)) - 4 is used to represent
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/// the LineSize bits.
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#define PPTT_ARM_CACHE_LINE_SIZE_MAX (1 << 11)
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#define PPTT_ARM_CACHE_LINE_SIZE_MIN (1 << 4)
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#endif // if defined (MDE_CPU_ARM) || defined (MDE_CPU_AARCH64)
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#endif // PPTT_PARSER_H_
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