34b162d078
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1621 According to Intel SDM as below, the BIT0 should be treated as lock bit, and BIT1 should be treated as disable(1)/enable(0) bit. "11b: AES instructions are not available until next RESET. Otherwise, AES instructions are available. If the configuration is not 01b, AES instructions can be mis-configured if a privileged agent unintentionally writes 11b" Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
132 lines
4.9 KiB
C
132 lines
4.9 KiB
C
/** @file
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AESNI feature.
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Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "CpuCommonFeatures.h"
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/**
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Prepares for the data used by CPU feature detection and initialization.
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@param[in] NumberOfProcessors The number of CPUs in the platform.
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@return Pointer to a buffer of CPU related configuration data.
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@note This service could be called by BSP only.
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**/
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VOID *
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EFIAPI
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AesniGetConfigData (
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IN UINTN NumberOfProcessors
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)
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{
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UINT64 *ConfigData;
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ConfigData = AllocateZeroPool (sizeof (UINT64) * NumberOfProcessors);
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ASSERT (ConfigData != NULL);
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return ConfigData;
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}
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/**
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Detects if AESNI feature supported on current processor.
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@param[in] ProcessorNumber The index of the CPU executing this function.
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@param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
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structure for the CPU executing this function.
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@param[in] ConfigData A pointer to the configuration buffer returned
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by CPU_FEATURE_GET_CONFIG_DATA. NULL if
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CPU_FEATURE_GET_CONFIG_DATA was not provided in
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RegisterCpuFeature().
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@retval TRUE AESNI feature is supported.
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@retval FALSE AESNI feature is not supported.
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@note This service could be called by BSP/APs.
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**/
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BOOLEAN
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EFIAPI
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AesniSupport (
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IN UINTN ProcessorNumber,
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IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
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IN VOID *ConfigData OPTIONAL
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)
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{
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MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig;
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if (CpuInfo->CpuIdVersionInfoEcx.Bits.AESNI == 1) {
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if (IS_SANDY_BRIDGE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
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IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
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IS_XEON_5600_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
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IS_XEON_E7_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
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IS_XEON_PHI_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
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MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *) ConfigData;
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ASSERT (MsrFeatureConfig != NULL);
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MsrFeatureConfig[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);
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}
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return TRUE;
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}
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return FALSE;
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}
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/**
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Initializes AESNI feature to specific state.
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@param[in] ProcessorNumber The index of the CPU executing this function.
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@param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
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structure for the CPU executing this function.
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@param[in] ConfigData A pointer to the configuration buffer returned
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by CPU_FEATURE_GET_CONFIG_DATA. NULL if
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CPU_FEATURE_GET_CONFIG_DATA was not provided in
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RegisterCpuFeature().
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@param[in] State If TRUE, then the AESNI feature must be enabled.
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If FALSE, then the AESNI feature must be disabled.
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@retval RETURN_SUCCESS AESNI feature is initialized.
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@note This service could be called by BSP only.
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**/
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RETURN_STATUS
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EFIAPI
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AesniInitialize (
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IN UINTN ProcessorNumber,
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IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
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IN VOID *ConfigData, OPTIONAL
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IN BOOLEAN State
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)
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{
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MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig;
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//
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// SANDY_BRIDGE, SILVERMONT, XEON_5600, XEON_7, and XEON_PHI have the same MSR index,
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// Simply use MSR_SANDY_BRIDGE_FEATURE_CONFIG here
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//
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// The scope of the MSR_SANDY_BRIDGE_FEATURE_CONFIG is Core, only program MSR_FEATURE_CONFIG for thread 0
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// of each core. Otherwise, once a thread in the core disabled AES, the other thread will cause GP when
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// programming it.
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//
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if (CpuInfo->ProcessorInfo.Location.Thread == 0) {
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MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *) ConfigData;
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ASSERT (MsrFeatureConfig != NULL);
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if ((MsrFeatureConfig[ProcessorNumber].Bits.AESConfiguration & BIT0) == 0) {
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CPU_REGISTER_TABLE_WRITE_FIELD (
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ProcessorNumber,
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Msr,
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MSR_SANDY_BRIDGE_FEATURE_CONFIG,
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MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER,
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Bits.AESConfiguration,
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BIT0 | ((State) ? 0 : BIT1)
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);
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}
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}
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return RETURN_SUCCESS;
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}
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