351b49c1a7
Unlike "gSmmCr3" in the previous patch, "gSmmCr4" is not only used for machine code patching, but also as a means to communicate the initial CR4 value from SmmRelocateBases() to InitSmmS3ResumeState(). In other words, the last four bytes of the "mov eax, Cr4Value" instruction's binary representation are utilized as normal data too. In order to get rid of the DB for "mov eax, Cr4Value", we have to split both roles, patching and data flow. Introduce the "mSmmCr4" global (SMRAM) variable for the data flow purpose. Rename the "gSmmCr4" variable to "gPatchSmmCr4" so that its association with PatchInstructionX86() is clear from the declaration, change its type to X86_ASSEMBLY_PATCH_LABEL, and patch it with PatchInstructionX86(), to the value now contained in "mSmmCr4". This lets us remove the binary (DB) encoding of "mov eax, Cr4Value" in "SmmInit.nasm". Cc: Eric Dong <eric.dong@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
151 lines
4.4 KiB
NASM
151 lines
4.4 KiB
NASM
;------------------------------------------------------------------------------ ;
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; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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; Module Name:
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;
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; SmmInit.nasm
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;
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; Abstract:
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;
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; Functions for relocating SMBASE's for all processors
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;
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;-------------------------------------------------------------------------------
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extern ASM_PFX(SmmInitHandler)
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extern ASM_PFX(mRebasedFlag)
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extern ASM_PFX(mSmmRelocationOriginalAddress)
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global ASM_PFX(gPatchSmmCr3)
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global ASM_PFX(gPatchSmmCr4)
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global ASM_PFX(gSmmCr0)
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global ASM_PFX(gSmmJmpAddr)
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global ASM_PFX(gSmmInitStack)
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global ASM_PFX(gcSmiInitGdtr)
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global ASM_PFX(gcSmmInitSize)
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global ASM_PFX(gcSmmInitTemplate)
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global ASM_PFX(mRebasedFlagAddr32)
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global ASM_PFX(mSmmRelocationOriginalAddressPtr32)
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DEFAULT REL
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SECTION .text
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ASM_PFX(gcSmiInitGdtr):
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DW 0
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DQ 0
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global ASM_PFX(SmmStartup)
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BITS 16
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ASM_PFX(SmmStartup):
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mov eax, 0x80000001 ; read capability
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cpuid
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mov ebx, edx ; rdmsr will change edx. keep it in ebx.
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mov eax, strict dword 0 ; source operand will be patched
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ASM_PFX(gPatchSmmCr3):
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mov cr3, eax
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o32 lgdt [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
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mov eax, strict dword 0 ; source operand will be patched
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ASM_PFX(gPatchSmmCr4):
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or ah, 2 ; enable XMM registers access
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mov cr4, eax
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mov ecx, 0xc0000080 ; IA32_EFER MSR
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rdmsr
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or ah, BIT0 ; set LME bit
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test ebx, BIT20 ; check NXE capability
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jz .1
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or ah, BIT3 ; set NXE bit
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.1:
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wrmsr
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DB 0x66, 0xb8 ; mov eax, imm32
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ASM_PFX(gSmmCr0): DD 0
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mov cr0, eax ; enable protected mode & paging
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DB 0x66, 0xea ; far jmp to long mode
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ASM_PFX(gSmmJmpAddr): DQ 0;@LongMode
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BITS 64
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@LongMode: ; long-mode starts here
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DB 0x48, 0xbc ; mov rsp, imm64
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ASM_PFX(gSmmInitStack): DQ 0
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and sp, 0xfff0 ; make sure RSP is 16-byte aligned
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;
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; Accoring to X64 calling convention, XMM0~5 are volatile, we need to save
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; them before calling C-function.
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;
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sub rsp, 0x60
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movdqa [rsp], xmm0
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movdqa [rsp + 0x10], xmm1
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movdqa [rsp + 0x20], xmm2
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movdqa [rsp + 0x30], xmm3
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movdqa [rsp + 0x40], xmm4
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movdqa [rsp + 0x50], xmm5
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add rsp, -0x20
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call ASM_PFX(SmmInitHandler)
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add rsp, 0x20
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;
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; Restore XMM0~5 after calling C-function.
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;
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movdqa xmm0, [rsp]
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movdqa xmm1, [rsp + 0x10]
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movdqa xmm2, [rsp + 0x20]
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movdqa xmm3, [rsp + 0x30]
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movdqa xmm4, [rsp + 0x40]
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movdqa xmm5, [rsp + 0x50]
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rsm
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BITS 16
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ASM_PFX(gcSmmInitTemplate):
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mov ebp, [cs:@L1 - ASM_PFX(gcSmmInitTemplate) + 0x8000]
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sub ebp, 0x30000
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jmp ebp
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@L1:
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DQ 0; ASM_PFX(SmmStartup)
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ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)
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BITS 64
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global ASM_PFX(SmmRelocationSemaphoreComplete)
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ASM_PFX(SmmRelocationSemaphoreComplete):
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push rax
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mov rax, [ASM_PFX(mRebasedFlag)]
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mov byte [rax], 1
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pop rax
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jmp [ASM_PFX(mSmmRelocationOriginalAddress)]
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;
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; Semaphore code running in 32-bit mode
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;
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global ASM_PFX(SmmRelocationSemaphoreComplete32)
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ASM_PFX(SmmRelocationSemaphoreComplete32):
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;
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; mov byte ptr [], 1
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;
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db 0xc6, 0x5
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ASM_PFX(mRebasedFlagAddr32): dd 0
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db 1
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;
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; jmp dword ptr []
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;
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db 0xff, 0x25
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ASM_PFX(mSmmRelocationOriginalAddressPtr32): dd 0
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global ASM_PFX(PiSmmCpuSmmInitFixupAddress)
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ASM_PFX(PiSmmCpuSmmInitFixupAddress):
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lea rax, [@LongMode]
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lea rcx, [ASM_PFX(gSmmJmpAddr)]
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mov qword [rcx], rax
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lea rax, [ASM_PFX(SmmStartup)]
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lea rcx, [@L1]
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mov qword [rcx], rax
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ret
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