3cbfba02fe
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
281 lines
11 KiB
Plaintext
281 lines
11 KiB
Plaintext
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/*-----------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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Intel Silvermont Processor Power Management BIOS Reference Code
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Copyright (c) 2006 - 2014, Intel Corporation
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Filename: CPU0CST.ASL
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Revision: Refer to Readme
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Date: Refer to Readme
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--------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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This Processor Power Management BIOS Source Code is furnished under license
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and may only be used or copied in accordance with the terms of the license.
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The information in this document is furnished for informational use only, is
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subject to change without notice, and should not be construed as a commitment
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by Intel Corporation. Intel Corporation assumes no responsibility or liability
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for any errors or inaccuracies that may appear in this document or any
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software that may be provided in association with this document.
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Except as permitted by such license, no part of this document may be
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reproduced, stored in a retrieval system, or transmitted in any form or by
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any means without the express written consent of Intel Corporation.
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WARNING: You are authorized and licensed to install and use this BIOS code
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ONLY on an IST PC. This utility may damage any system that does not
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meet these requirements.
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An IST PC is a computer which
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(1) Is capable of seamlessly and automatically transitioning among
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multiple performance states (potentially operating at different
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efficiency ratings) based upon power source changes, END user
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preference, processor performance demand, and thermal conditions; and
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(2) Includes an Intel Pentium II processors, Intel Pentium III
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processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
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Processor-M, Intel Pentium M Processor, or any other future Intel
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processors that incorporates the capability to transition between
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different performance states by altering some, or any combination of,
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the following processor attributes: core voltage, core frequency, bus
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frequency, number of processor cores available, or any other attribute
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that changes the efficiency (instructions/unit time-power) at which the
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processor operates.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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NOTES:
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(1) <TODO> - IF the trap range and port definitions do not match those
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specified by this reference code, this file must be modified IAW the
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individual implmentation.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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DefinitionBlock (
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"CPU0CST.aml",
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"SSDT",
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1,
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"PmRef",
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"Cpu0Cst",
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0x3001
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)
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{
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External(\_PR.CPU0, DeviceObj)
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External(PWRS)
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External(CFGD)
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External(PDC0)
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Scope(\_PR.CPU0)
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{
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OperationRegion (DEB0, SystemIO, 0x80, 1) //DBG
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Field (DEB0, ByteAcc,NoLock,Preserve) //DBG
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{ DBG8, 8,} //DBG
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Method (_CST, 0)
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{
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Store(0x60,DBG8) //DBG
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// IF CMP is supported, but independent C-States beyond C1 are
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// not supported; return C1 Halt and rely on BIOS based software
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// coordination
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//
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// CFGD[24] = CMP support
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// PDCx[4] = 0 - OS does not support ind. C2/C3 in MP systems
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//
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// Note: SMI will be generated when both processor enter the
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// Halt state.
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//
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If(LAnd(And(CFGD,0x01000000), LNot(And(PDC0,0x10))))
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{
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Store(0x61,DBG8) //DBG
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Return(Package() {
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1,
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Package()
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{ // C1 halt, but with BIOS coordination
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ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
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1,
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157,
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1000
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}
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})
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}
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// IF MWAIT extensions are supported, use them.
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//
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// IF C6 capable/enabled AND Battery
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// Report MWAIT C1, C2, C6 w/ BM_STS avoidance
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// ELSE IF C4 capable/enabled AND Battery
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// Report MWAIT C1, C2, C4 w/ BM_STS avoidance
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// ELSE IF C3 capable/enabled
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// Report MWAIT C1, C2, C3 w/ BM_STS avoidance
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// ELSE IF C2 capable/enabled
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// Report MWAIT C1, C2
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// ELSE
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// Report MWAIT C1
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//
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// CFGD[21] = 1 - MWAIT extensions supported
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// CFGD[13] = 1 - C7 Capable/Enabled
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// CFGD[12] = 1 - C6S Capable/Enabled
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// CFGD[11] = 1 - C6 Capable/Enabled
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// CFGD[7] = 1 - C4 Capable/Enabled
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// CFGD[5] = 1 - C3 Capable/Enabled
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// PDCx[9] = 1 - OS supports MWAIT extensions
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// PDCx[8] = 1 - OS supports MWAIT for C1
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// (Inferred from PDCx[9] = 1.)
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// PDCx[4] = 1 - OS supports independent C2/C3 in MP systems
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// or
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// NOT CMP (Inferred from previous check.)
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//
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If(LAnd(And(CFGD, 0x200000), And(PDC0,0x200)))
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{
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//
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// <TODO> The implementor may wish to only report C1-C2
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// when on AC power. In this case, the IF clause below can
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// be modified to something like:
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//
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// "If(LAnd(And(CFGD,0x200), LNot(PWRS)))"
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//
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// Which uses the power state of the system (PWRS) to
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// determine whether to allow deepers states.
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//
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// IF C7 supported AND on battery
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// report MWAIT C1, C6, C7
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//
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// CFGD[13] = C7 Capable/Enabled
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// CFGD[11] = C6 Capable/Enabled
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//
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If(LAnd(And(CFGD,0x2000),And(CFGD,0x40000000)))
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{
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Store(0x77,DBG8) //DBG
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Return( Package()
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{
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3,
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Package()
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{ // C1, MWAIT
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ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
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1,
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1,
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1000
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},
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Package()
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{
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// C6, MWAIT Extension with Incremental L2 Shrink
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// ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},
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// C6, MWAIT Extension with No L2 Shrink
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ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},
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2,
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500,
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10
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},
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Package()
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{
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// C7, MWAIT Extension with Full L2 Shrink
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ResourceTemplate(){Register(FFixedHW, 1, 2, 0x64, 1)},
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3,
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1500, //PnP setting, 1.5 ms for worst-case exit latency
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10
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}
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})
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}
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If(LAnd(And(CFGD,0x2000),LNot(And(CFGD,0x40000000))))
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{
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Store(0x67,DBG8) //DBG
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Return( Package()
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{
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3,
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Package()
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{ // C1, MWAIT
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ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
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1,
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1,
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1000
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},
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Package()
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{
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// C6, MWAIT Extension with Incremental L2 Shrink
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// ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},
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// C6 = C6NS, MWAIT Extension with No L2 Shrink
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ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},
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2,
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500,
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10
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},
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Package()
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{
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ResourceTemplate(){Register(FFixedHW, 1, 2, 0x52, 1)},
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3,
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1500, //PnP setting, 1.5 ms for worst-case exit latency
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10
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}
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})
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}
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If(And(CFGD,0x800)) // Setup Max C-State = C6
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{
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Store(0x76,DBG8) //DBG
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Return( Package()
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{
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2,
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Package()
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{ // C1, MWAIT
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ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
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1,
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1,
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1000
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},
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Package()
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{
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// C6, MWAIT Extension with Incremental L2 Shrink
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// ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},
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// C6, MWAIT Extension with No L2 Shrink
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ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},
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2,
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500,
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10
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}
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})
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}
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//
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// IF no deeper C-States are supported; report MWAIT C1.
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//
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Store(0x71,DBG8) //DBG
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Return(Package()
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{
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1,
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Package()
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{ // C1, MWAIT
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ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
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1,
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1,
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1000
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}
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})
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}
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}
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}
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}
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