397bdc990b
... and also rename the ArmGicLib sources to use an explicit 'Lib' suffix. The renaming did not work well with SVN. Files were missing from the initial commit. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15622 6f19259b-4bc3-4df7-8a09-765794883524
123 lines
3.0 KiB
C
123 lines
3.0 KiB
C
/** @file
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*
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* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Uefi.h>
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#include <Library/IoLib.h>
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#include <Library/ArmGicLib.h>
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#include <Library/PcdLib.h>
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UINTN
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EFIAPI
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ArmGicGetInterfaceIdentification (
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IN INTN GicInterruptInterfaceBase
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)
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{
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// Read the GIC Identification Register
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return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIIDR);
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}
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UINTN
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EFIAPI
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ArmGicGetMaxNumInterrupts (
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IN INTN GicDistributorBase
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)
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{
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return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);
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}
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VOID
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EFIAPI
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ArmGicSendSgiTo (
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IN INTN GicDistributorBase,
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IN INTN TargetListFilter,
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IN INTN CPUTargetList,
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IN INTN SgiId
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)
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{
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MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId);
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}
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UINTN
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EFIAPI
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ArmGicAcknowledgeInterrupt (
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IN UINTN GicInterruptInterfaceBase
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)
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{
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// Read the Interrupt Acknowledge Register
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return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
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}
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VOID
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EFIAPI
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ArmGicEndOfInterrupt (
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IN UINTN GicInterruptInterfaceBase,
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IN UINTN Source
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)
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{
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Source);
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}
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VOID
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EFIAPI
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ArmGicEnableInterrupt (
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IN UINTN GicDistributorBase,
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IN UINTN Source
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)
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{
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UINT32 RegOffset;
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UINTN RegShift;
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// Calculate enable register offset and bit position
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RegOffset = Source / 32;
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RegShift = Source % 32;
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// Write set-enable register
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MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift);
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}
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VOID
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EFIAPI
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ArmGicDisableInterrupt (
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IN UINTN GicDistributorBase,
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IN UINTN Source
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)
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{
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UINT32 RegOffset;
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UINTN RegShift;
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// Calculate enable register offset and bit position
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RegOffset = Source / 32;
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RegShift = Source % 32;
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// Write clear-enable register
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MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift);
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}
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BOOLEAN
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EFIAPI
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ArmGicIsInterruptEnabled (
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IN UINTN GicDistributorBase,
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IN UINTN Source
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)
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{
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UINT32 RegOffset;
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UINTN RegShift;
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// Calculate enable register offset and bit position
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RegOffset = Source / 32;
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RegShift = Source % 32;
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return ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0);
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}
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