3dd47f9544
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863 From this patch we start to restruct the functions which set PCDs into two, one for PlatformInitLib, one for PlatformPei. AddressWidthInitialization is the first one. It is splitted into two: - PlatformAddressWidthInitialization is for PlatformInitLib - AddressWidthInitialization is for PlatformPei. It calls PlatformAddressWidthInitialization then set PCDs. Below functions are also refined for PlatformInitLib: - PlatformScanOrAdd64BitE820Ram - PlatformGetSystemMemorySizeAbove4gb - PlatformGetFirstNonAddress All the SetPcd codes are removed from above functions. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Sebastien Boeuf <sebastien.boeuf@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
797 lines
24 KiB
C
797 lines
24 KiB
C
/**@file
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Platform PEI driver
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Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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//
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// The package level header files this module uses
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//
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#include <PiPei.h>
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//
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// The Library classes this module consumes
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//
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#include <Library/BaseMemoryLib.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PciLib.h>
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#include <Library/PeimEntryPoint.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/QemuFwCfgLib.h>
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#include <Library/QemuFwCfgS3Lib.h>
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#include <Library/QemuFwCfgSimpleParserLib.h>
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#include <Library/ResourcePublicationLib.h>
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#include <Ppi/MasterBootMode.h>
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#include <IndustryStandard/I440FxPiix4.h>
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#include <IndustryStandard/Microvm.h>
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#include <IndustryStandard/Pci22.h>
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#include <IndustryStandard/Q35MchIch9.h>
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#include <IndustryStandard/QemuCpuHotplug.h>
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#include <Library/MemEncryptSevLib.h>
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#include <OvmfPlatforms.h>
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#include "Platform.h"
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EFI_HOB_PLATFORM_INFO mPlatformInfoHob = { 0 };
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EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
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{
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EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
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&gEfiPeiMasterBootModePpiGuid,
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NULL
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}
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};
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VOID
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MemMapInitialization (
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IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
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)
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{
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UINT64 PciIoBase;
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UINT64 PciIoSize;
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RETURN_STATUS PcdStatus;
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UINT32 TopOfLowRam;
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UINT64 PciExBarBase;
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UINT32 PciBase;
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UINT32 PciSize;
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PciIoBase = 0xC000;
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PciIoSize = 0x4000;
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//
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// Video memory + Legacy BIOS region
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//
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PlatformAddIoMemoryRangeHob (0x0A0000, BASE_1MB);
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if (PlatformInfoHob->HostBridgeDevId == 0xffff /* microvm */) {
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PlatformAddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB);
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PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */
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PlatformAddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */
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return;
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}
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TopOfLowRam = GetSystemMemorySizeBelow4gb (PlatformInfoHob);
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PciExBarBase = 0;
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if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
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//
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// The MMCONFIG area is expected to fall between the top of low RAM and
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// the base of the 32-bit PCI host aperture.
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//
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PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
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ASSERT (TopOfLowRam <= PciExBarBase);
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ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
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PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
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} else {
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ASSERT (TopOfLowRam <= PlatformInfoHob->Uc32Base);
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PciBase = PlatformInfoHob->Uc32Base;
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}
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//
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// address purpose size
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// ------------ -------- -------------------------
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// max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
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// 0xFC000000 gap 44 MB
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// 0xFEC00000 IO-APIC 4 KB
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// 0xFEC01000 gap 1020 KB
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// 0xFED00000 HPET 1 KB
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// 0xFED00400 gap 111 KB
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// 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB
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// 0xFED20000 gap 896 KB
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// 0xFEE00000 LAPIC 1 MB
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//
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PciSize = 0xFC000000 - PciBase;
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PlatformAddIoMemoryBaseSizeHob (PciBase, PciSize);
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PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);
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ASSERT_RETURN_ERROR (PcdStatus);
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PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);
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ASSERT_RETURN_ERROR (PcdStatus);
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PlatformInfoHob->PcdPciMmio32Base = PciBase;
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PlatformInfoHob->PcdPciMmio32Size = PciSize;
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PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
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PlatformAddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
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if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
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PlatformAddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
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//
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// Note: there should be an
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//
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// PlatformAddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
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//
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// call below, just like the one above for RCBA. However, Linux insists
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// that the MMCONFIG area be marked in the E820 or UEFI memory map as
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// "reserved memory" -- Linux does not content itself with a simple gap
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// in the memory map wherever the MCFG ACPI table points to.
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//
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// This appears to be a safety measure. The PCI Firmware Specification
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// (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
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// *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
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// [...]". (Emphasis added here.)
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//
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// Normally we add memory resource descriptor HOBs in
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// QemuInitializeRam(), and pre-allocate from those with memory
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// allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
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// is most definitely not RAM; so, as an exception, cover it with
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// uncacheable reserved memory right here.
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//
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PlatformAddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
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BuildMemoryAllocationHob (
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PciExBarBase,
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SIZE_256MB,
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EfiReservedMemoryType
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);
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}
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PlatformAddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB);
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//
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// On Q35, the IO Port space is available for PCI resource allocations from
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// 0x6000 up.
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//
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if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
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PciIoBase = 0x6000;
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PciIoSize = 0xA000;
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ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);
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}
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//
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// Add PCI IO Port space available for PCI resource allocations.
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//
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BuildResourceDescriptorHob (
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EFI_RESOURCE_IO,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
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PciIoBase,
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PciIoSize
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);
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PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);
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ASSERT_RETURN_ERROR (PcdStatus);
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PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);
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ASSERT_RETURN_ERROR (PcdStatus);
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PlatformInfoHob->PcdPciIoBase = PciIoBase;
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PlatformInfoHob->PcdPciIoSize = PciIoSize;
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}
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#define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \
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do { \
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BOOLEAN Setting; \
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RETURN_STATUS PcdStatus; \
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\
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if (!RETURN_ERROR (QemuFwCfgParseBool ( \
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"opt/ovmf/" #TokenName, &Setting))) { \
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PcdStatus = PcdSetBoolS (TokenName, Setting); \
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ASSERT_RETURN_ERROR (PcdStatus); \
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} \
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} while (0)
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VOID
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NoexecDxeInitialization (
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VOID
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)
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{
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UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);
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}
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VOID
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PciExBarInitialization (
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VOID
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)
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{
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union {
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UINT64 Uint64;
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UINT32 Uint32[2];
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} PciExBarBase;
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//
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// We only support the 256MB size for the MMCONFIG area:
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// 256 buses * 32 devices * 8 functions * 4096 bytes config space.
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//
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// The masks used below enforce the Q35 requirements that the MMCONFIG area
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// be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
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//
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// Note that (b) also ensures that the minimum address width we have
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// determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
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// for DXE's page tables to cover the MMCONFIG area.
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//
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PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);
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ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);
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ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);
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//
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// Clear the PCIEXBAREN bit first, before programming the high register.
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//
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PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);
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//
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// Program the high register. Then program the low register, setting the
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// MMCONFIG area size and enabling decoding at once.
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//
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PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);
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PciWrite32 (
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DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),
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PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN
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);
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}
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static const UINT8 EmptyFdt[] = {
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0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x00, 0x48,
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0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x48,
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0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11,
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0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x09,
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};
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VOID
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MicrovmInitialization (
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VOID
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)
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{
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FIRMWARE_CONFIG_ITEM FdtItem;
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UINTN FdtSize;
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UINTN FdtPages;
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EFI_STATUS Status;
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UINT64 *FdtHobData;
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VOID *NewBase;
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Status = QemuFwCfgFindFile ("etc/fdt", &FdtItem, &FdtSize);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_INFO, "%a: no etc/fdt found in fw_cfg, using dummy\n", __FUNCTION__));
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FdtItem = 0;
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FdtSize = sizeof (EmptyFdt);
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}
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FdtPages = EFI_SIZE_TO_PAGES (FdtSize);
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NewBase = AllocatePages (FdtPages);
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if (NewBase == NULL) {
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DEBUG ((DEBUG_INFO, "%a: AllocatePages failed\n", __FUNCTION__));
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return;
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}
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if (FdtItem) {
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QemuFwCfgSelectItem (FdtItem);
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QemuFwCfgReadBytes (FdtSize, NewBase);
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} else {
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CopyMem (NewBase, EmptyFdt, FdtSize);
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}
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FdtHobData = BuildGuidHob (&gFdtHobGuid, sizeof (*FdtHobData));
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if (FdtHobData == NULL) {
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DEBUG ((DEBUG_INFO, "%a: BuildGuidHob failed\n", __FUNCTION__));
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return;
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}
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DEBUG ((
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DEBUG_INFO,
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"%a: fdt at 0x%x (size %d)\n",
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__FUNCTION__,
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NewBase,
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FdtSize
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));
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*FdtHobData = (UINTN)NewBase;
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}
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VOID
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MiscInitializationForMicrovm (
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IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
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)
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{
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RETURN_STATUS PcdStatus;
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ASSERT (PlatformInfoHob->HostBridgeDevId == 0xffff);
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DEBUG ((DEBUG_INFO, "%a: microvm\n", __FUNCTION__));
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//
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// Disable A20 Mask
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//
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IoOr8 (0x92, BIT1);
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//
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// Build the CPU HOB with guest RAM size dependent address width and 16-bits
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// of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
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// S3 resume as well, so we build it unconditionally.)
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//
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BuildCpuHob (PlatformInfoHob->PhysMemAddressWidth, 16);
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MicrovmInitialization ();
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PcdStatus = PcdSet16S (
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PcdOvmfHostBridgePciDevId,
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MICROVM_PSEUDO_DEVICE_ID
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);
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ASSERT_RETURN_ERROR (PcdStatus);
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}
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VOID
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MiscInitialization (
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IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
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)
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{
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UINTN PmCmd;
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UINTN Pmba;
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UINT32 PmbaAndVal;
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UINT32 PmbaOrVal;
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UINTN AcpiCtlReg;
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UINT8 AcpiEnBit;
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RETURN_STATUS PcdStatus;
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//
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// Disable A20 Mask
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//
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IoOr8 (0x92, BIT1);
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//
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// Build the CPU HOB with guest RAM size dependent address width and 16-bits
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// of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
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// S3 resume as well, so we build it unconditionally.)
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//
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BuildCpuHob (PlatformInfoHob->PhysMemAddressWidth, 16);
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//
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// Determine platform type and save Host Bridge DID to PCD
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//
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switch (PlatformInfoHob->HostBridgeDevId) {
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case INTEL_82441_DEVICE_ID:
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PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
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Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
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PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
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PmbaOrVal = PIIX4_PMBA_VALUE;
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AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
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AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
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break;
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case INTEL_Q35_MCH_DEVICE_ID:
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PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
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Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
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PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
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PmbaOrVal = ICH9_PMBASE_VALUE;
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AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
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AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;
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break;
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case CLOUDHV_DEVICE_ID:
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break;
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default:
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DEBUG ((
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DEBUG_ERROR,
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"%a: Unknown Host Bridge Device ID: 0x%04x\n",
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__FUNCTION__,
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PlatformInfoHob->HostBridgeDevId
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));
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ASSERT (FALSE);
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return;
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}
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PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, PlatformInfoHob->HostBridgeDevId);
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ASSERT_RETURN_ERROR (PcdStatus);
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if (PlatformInfoHob->HostBridgeDevId == CLOUDHV_DEVICE_ID) {
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DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor is done.\n", __FUNCTION__));
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return;
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}
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//
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// If the appropriate IOspace enable bit is set, assume the ACPI PMBA has
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// been configured and skip the setup here. This matches the logic in
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// AcpiTimerLibConstructor ().
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//
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if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
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//
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// The PEI phase should be exited with fully accessibe ACPI PM IO space:
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// 1. set PMBA
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//
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PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
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//
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// 2. set PCICMD/IOSE
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//
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PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
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//
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// 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
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//
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PciOr8 (AcpiCtlReg, AcpiEnBit);
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}
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if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
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//
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// Set Root Complex Register Block BAR
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//
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PciWrite32 (
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POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
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ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
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);
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//
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// Set PCI Express Register Range Base Address
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//
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PciExBarInitialization ();
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}
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}
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VOID
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BootModeInitialization (
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IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
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)
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{
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EFI_STATUS Status;
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if (PlatformCmosRead8 (0xF) == 0xFE) {
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PlatformInfoHob->BootMode = BOOT_ON_S3_RESUME;
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}
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PlatformCmosWrite8 (0xF, 0x00);
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Status = PeiServicesSetBootMode (PlatformInfoHob->BootMode);
|
|
ASSERT_EFI_ERROR (Status);
|
|
|
|
Status = PeiServicesInstallPpi (mPpiBootMode);
|
|
ASSERT_EFI_ERROR (Status);
|
|
}
|
|
|
|
VOID
|
|
ReserveEmuVariableNvStore (
|
|
)
|
|
{
|
|
EFI_PHYSICAL_ADDRESS VariableStore;
|
|
RETURN_STATUS PcdStatus;
|
|
|
|
//
|
|
// Allocate storage for NV variables early on so it will be
|
|
// at a consistent address. Since VM memory is preserved
|
|
// across reboots, this allows the NV variable storage to survive
|
|
// a VM reboot.
|
|
//
|
|
VariableStore =
|
|
(EFI_PHYSICAL_ADDRESS)(UINTN)
|
|
AllocateRuntimePages (
|
|
EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))
|
|
);
|
|
DEBUG ((
|
|
DEBUG_INFO,
|
|
"Reserved variable store memory: 0x%lX; size: %dkb\n",
|
|
VariableStore,
|
|
(2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
|
|
));
|
|
PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);
|
|
ASSERT_RETURN_ERROR (PcdStatus);
|
|
}
|
|
|
|
VOID
|
|
S3Verification (
|
|
VOID
|
|
)
|
|
{
|
|
#if defined (MDE_CPU_X64)
|
|
if (mPlatformInfoHob.SmmSmramRequire && mPlatformInfoHob.S3Supported) {
|
|
DEBUG ((
|
|
DEBUG_ERROR,
|
|
"%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n",
|
|
__FUNCTION__
|
|
));
|
|
DEBUG ((
|
|
DEBUG_ERROR,
|
|
"%a: Please disable S3 on the QEMU command line (see the README),\n",
|
|
__FUNCTION__
|
|
));
|
|
DEBUG ((
|
|
DEBUG_ERROR,
|
|
"%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n",
|
|
__FUNCTION__
|
|
));
|
|
ASSERT (FALSE);
|
|
CpuDeadLoop ();
|
|
}
|
|
|
|
#endif
|
|
}
|
|
|
|
VOID
|
|
Q35BoardVerification (
|
|
VOID
|
|
)
|
|
{
|
|
if (mPlatformInfoHob.HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
|
|
return;
|
|
}
|
|
|
|
DEBUG ((
|
|
DEBUG_ERROR,
|
|
"%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "
|
|
"only DID=0x%04x (Q35) is supported\n",
|
|
__FUNCTION__,
|
|
mPlatformInfoHob.HostBridgeDevId,
|
|
INTEL_Q35_MCH_DEVICE_ID
|
|
));
|
|
ASSERT (FALSE);
|
|
CpuDeadLoop ();
|
|
}
|
|
|
|
/**
|
|
Fetch the boot CPU count and the possible CPU count from QEMU, and expose
|
|
them to UefiCpuPkg modules. Set the mMaxCpuCount variable.
|
|
**/
|
|
VOID
|
|
MaxCpuCountInitialization (
|
|
IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
|
|
)
|
|
{
|
|
UINT16 BootCpuCount;
|
|
UINT32 MaxCpuCount;
|
|
RETURN_STATUS PcdStatus;
|
|
|
|
//
|
|
// Try to fetch the boot CPU count.
|
|
//
|
|
QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);
|
|
BootCpuCount = QemuFwCfgRead16 ();
|
|
if (BootCpuCount == 0) {
|
|
//
|
|
// QEMU doesn't report the boot CPU count. (BootCpuCount == 0) will let
|
|
// MpInitLib count APs up to (PcdCpuMaxLogicalProcessorNumber - 1), or
|
|
// until PcdCpuApInitTimeOutInMicroSeconds elapses (whichever is reached
|
|
// first).
|
|
//
|
|
DEBUG ((DEBUG_WARN, "%a: boot CPU count unavailable\n", __FUNCTION__));
|
|
MaxCpuCount = PlatformInfoHob->DefaultMaxCpuNumber;
|
|
} else {
|
|
//
|
|
// We will expose BootCpuCount to MpInitLib. MpInitLib will count APs up to
|
|
// (BootCpuCount - 1) precisely, regardless of timeout.
|
|
//
|
|
// Now try to fetch the possible CPU count.
|
|
//
|
|
UINTN CpuHpBase;
|
|
UINT32 CmdData2;
|
|
|
|
CpuHpBase = ((PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) ?
|
|
ICH9_CPU_HOTPLUG_BASE : PIIX4_CPU_HOTPLUG_BASE);
|
|
|
|
//
|
|
// If only legacy mode is available in the CPU hotplug register block, or
|
|
// the register block is completely missing, then the writes below are
|
|
// no-ops.
|
|
//
|
|
// 1. Switch the hotplug register block to modern mode.
|
|
//
|
|
IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);
|
|
//
|
|
// 2. Select a valid CPU for deterministic reading of
|
|
// QEMU_CPUHP_R_CMD_DATA2.
|
|
//
|
|
// CPU#0 is always valid; it is the always present and non-removable
|
|
// BSP.
|
|
//
|
|
IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);
|
|
//
|
|
// 3. Send a command after which QEMU_CPUHP_R_CMD_DATA2 is specified to
|
|
// read as zero, and which does not invalidate the selector. (The
|
|
// selector may change, but it must not become invalid.)
|
|
//
|
|
// Send QEMU_CPUHP_CMD_GET_PENDING, as it will prove useful later.
|
|
//
|
|
IoWrite8 (CpuHpBase + QEMU_CPUHP_W_CMD, QEMU_CPUHP_CMD_GET_PENDING);
|
|
//
|
|
// 4. Read QEMU_CPUHP_R_CMD_DATA2.
|
|
//
|
|
// If the register block is entirely missing, then this is an unassigned
|
|
// IO read, returning all-bits-one.
|
|
//
|
|
// If only legacy mode is available, then bit#0 stands for CPU#0 in the
|
|
// "CPU present bitmap". CPU#0 is always present.
|
|
//
|
|
// Otherwise, QEMU_CPUHP_R_CMD_DATA2 is either still reserved (returning
|
|
// all-bits-zero), or it is specified to read as zero after the above
|
|
// steps. Both cases confirm modern mode.
|
|
//
|
|
CmdData2 = IoRead32 (CpuHpBase + QEMU_CPUHP_R_CMD_DATA2);
|
|
DEBUG ((DEBUG_VERBOSE, "%a: CmdData2=0x%x\n", __FUNCTION__, CmdData2));
|
|
if (CmdData2 != 0) {
|
|
//
|
|
// QEMU doesn't support the modern CPU hotplug interface. Assume that the
|
|
// possible CPU count equals the boot CPU count (precluding hotplug).
|
|
//
|
|
DEBUG ((
|
|
DEBUG_WARN,
|
|
"%a: modern CPU hotplug interface unavailable\n",
|
|
__FUNCTION__
|
|
));
|
|
MaxCpuCount = BootCpuCount;
|
|
} else {
|
|
//
|
|
// Grab the possible CPU count from the modern CPU hotplug interface.
|
|
//
|
|
UINT32 Present, Possible, Selected;
|
|
|
|
Present = 0;
|
|
Possible = 0;
|
|
|
|
//
|
|
// We've sent QEMU_CPUHP_CMD_GET_PENDING last; this ensures
|
|
// QEMU_CPUHP_RW_CMD_DATA can now be read usefully. However,
|
|
// QEMU_CPUHP_CMD_GET_PENDING may have selected a CPU with actual pending
|
|
// hotplug events; therefore, select CPU#0 forcibly.
|
|
//
|
|
IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);
|
|
|
|
do {
|
|
UINT8 CpuStatus;
|
|
|
|
//
|
|
// Read the status of the currently selected CPU. This will help with a
|
|
// sanity check against "BootCpuCount".
|
|
//
|
|
CpuStatus = IoRead8 (CpuHpBase + QEMU_CPUHP_R_CPU_STAT);
|
|
if ((CpuStatus & QEMU_CPUHP_STAT_ENABLED) != 0) {
|
|
++Present;
|
|
}
|
|
|
|
//
|
|
// Attempt to select the next CPU.
|
|
//
|
|
++Possible;
|
|
IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);
|
|
//
|
|
// If the selection is successful, then the following read will return
|
|
// the selector (which we know is positive at this point). Otherwise,
|
|
// the read will return 0.
|
|
//
|
|
Selected = IoRead32 (CpuHpBase + QEMU_CPUHP_RW_CMD_DATA);
|
|
ASSERT (Selected == Possible || Selected == 0);
|
|
} while (Selected > 0);
|
|
|
|
//
|
|
// Sanity check: fw_cfg and the modern CPU hotplug interface should
|
|
// return the same boot CPU count.
|
|
//
|
|
if (BootCpuCount != Present) {
|
|
DEBUG ((
|
|
DEBUG_WARN,
|
|
"%a: QEMU v2.7 reset bug: BootCpuCount=%d "
|
|
"Present=%u\n",
|
|
__FUNCTION__,
|
|
BootCpuCount,
|
|
Present
|
|
));
|
|
//
|
|
// The handling of QemuFwCfgItemSmpCpuCount, across CPU hotplug plus
|
|
// platform reset (including S3), was corrected in QEMU commit
|
|
// e3cadac073a9 ("pc: fix FW_CFG_NB_CPUS to account for -device added
|
|
// CPUs", 2016-11-16), part of release v2.8.0.
|
|
//
|
|
BootCpuCount = (UINT16)Present;
|
|
}
|
|
|
|
MaxCpuCount = Possible;
|
|
}
|
|
}
|
|
|
|
DEBUG ((
|
|
DEBUG_INFO,
|
|
"%a: BootCpuCount=%d MaxCpuCount=%u\n",
|
|
__FUNCTION__,
|
|
BootCpuCount,
|
|
MaxCpuCount
|
|
));
|
|
ASSERT (BootCpuCount <= MaxCpuCount);
|
|
|
|
PcdStatus = PcdSet32S (PcdCpuBootLogicalProcessorNumber, BootCpuCount);
|
|
ASSERT_RETURN_ERROR (PcdStatus);
|
|
PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, MaxCpuCount);
|
|
ASSERT_RETURN_ERROR (PcdStatus);
|
|
|
|
PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber = MaxCpuCount;
|
|
PlatformInfoHob->PcdCpuBootLogicalProcessorNumber = BootCpuCount;
|
|
}
|
|
|
|
/**
|
|
Perform Platform PEI initialization.
|
|
|
|
@param FileHandle Handle of the file being invoked.
|
|
@param PeiServices Describes the list of possible PEI Services.
|
|
|
|
@return EFI_SUCCESS The PEIM initialized successfully.
|
|
|
|
**/
|
|
EFI_STATUS
|
|
EFIAPI
|
|
InitializePlatform (
|
|
IN EFI_PEI_FILE_HANDLE FileHandle,
|
|
IN CONST EFI_PEI_SERVICES **PeiServices
|
|
)
|
|
{
|
|
EFI_STATUS Status;
|
|
|
|
DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));
|
|
|
|
mPlatformInfoHob.SmmSmramRequire = FeaturePcdGet (PcdSmmSmramRequire);
|
|
mPlatformInfoHob.SevEsIsEnabled = MemEncryptSevEsIsEnabled ();
|
|
mPlatformInfoHob.PcdPciMmio64Size = PcdGet64 (PcdPciMmio64Size);
|
|
mPlatformInfoHob.DefaultMaxCpuNumber = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
|
|
|
|
PlatformDebugDumpCmos ();
|
|
|
|
if (QemuFwCfgS3Enabled ()) {
|
|
DEBUG ((DEBUG_INFO, "S3 support was detected on QEMU\n"));
|
|
mPlatformInfoHob.S3Supported = TRUE;
|
|
Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
|
|
ASSERT_EFI_ERROR (Status);
|
|
}
|
|
|
|
S3Verification ();
|
|
BootModeInitialization (&mPlatformInfoHob);
|
|
AddressWidthInitialization (&mPlatformInfoHob);
|
|
|
|
//
|
|
// Query Host Bridge DID
|
|
//
|
|
mPlatformInfoHob.HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
|
|
|
|
MaxCpuCountInitialization (&mPlatformInfoHob);
|
|
|
|
if (mPlatformInfoHob.SmmSmramRequire) {
|
|
Q35BoardVerification ();
|
|
Q35TsegMbytesInitialization ();
|
|
Q35SmramAtDefaultSmbaseInitialization ();
|
|
}
|
|
|
|
PublishPeiMemory ();
|
|
|
|
QemuUc32BaseInitialization (&mPlatformInfoHob);
|
|
|
|
InitializeRamRegions (&mPlatformInfoHob);
|
|
|
|
if (mPlatformInfoHob.BootMode != BOOT_ON_S3_RESUME) {
|
|
if (!mPlatformInfoHob.SmmSmramRequire) {
|
|
ReserveEmuVariableNvStore ();
|
|
}
|
|
|
|
PeiFvInitialization ();
|
|
MemTypeInfoInitialization ();
|
|
MemMapInitialization (&mPlatformInfoHob);
|
|
NoexecDxeInitialization ();
|
|
}
|
|
|
|
InstallClearCacheCallback ();
|
|
AmdSevInitialize ();
|
|
if (mPlatformInfoHob.HostBridgeDevId == 0xffff) {
|
|
MiscInitializationForMicrovm (&mPlatformInfoHob);
|
|
} else {
|
|
MiscInitialization (&mPlatformInfoHob);
|
|
}
|
|
|
|
InstallFeatureControlCallback ();
|
|
|
|
return EFI_SUCCESS;
|
|
}
|