543add1d41
Changes to support spec changes 1. Remove usage of Pcd. 2. Change code to validate the Temporary Ram size input. 3. Consume the input saved in YMM Register Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chiu Chasel <chasel.chiu@intel.com> Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com> Cc: Ni Ray <ray.ni@intel.com> Signed-off-by: Duggapu Chinni B <chinni.b.duggapu@intel.com> Reviewed-by: Chiu Chasel <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
204 lines
4.8 KiB
PHP
204 lines
4.8 KiB
PHP
;------------------------------------------------------------------------------
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;
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; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Abstract:
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;
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; Provide macro for register save/restore using SSE registers
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;
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;------------------------------------------------------------------------------
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;
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; Define SSE instruction set
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;
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%ifdef USE_SSE41_FLAG
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;
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; Define SSE macros using SSE 4.1 instructions
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; args 1:XMM, 2:IDX, 3:REG
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%macro SXMMN 3
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pinsrd %1, %3, (%2 & 3)
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%endmacro
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;
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;args 1:XMM, 2:REG, 3:IDX
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;
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%macro LXMMN 3
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pextrd %2, %1, (%3 & 3)
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%endmacro
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%else
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;
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; Define SSE macros using SSE 2 instructions
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; args 1:XMM, 2:IDX, 3:REG
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%macro SXMMN 3
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pinsrw %1, %3, (%2 & 3) * 2
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ror %3, 16
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pinsrw %1, %3, (%2 & 3) * 2 + 1
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rol %3, 16
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%endmacro
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;
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;args 1:XMM, 2:REG, 3:IDX
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;
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%macro LXMMN 3
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pshufd %1, %1, ((0E4E4E4h >> (%3 * 2)) & 0FFh)
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movd %2, %1
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pshufd %1, %1, ((0E4E4E4h >> (%3 * 2 + (%3 & 1) * 4)) & 0FFh)
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%endmacro
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%endif
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;
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; XMM7 to save/restore EBP - slot 0, EBX - slot 1, ESI - slot 2, EDI - slot 3
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;
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%macro SAVE_REGS 0
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SXMMN xmm7, 0, ebp
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SXMMN xmm7, 1, ebx
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SXMMN xmm7, 2, esi
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SXMMN xmm7, 3, edi
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SAVE_ESP
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%endmacro
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%macro LOAD_REGS 0
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LXMMN xmm7, ebp, 0
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LXMMN xmm7, ebx, 1
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LXMMN xmm7, esi, 2
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LXMMN xmm7, edi, 3
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LOAD_ESP
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%endmacro
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;
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; XMM6 to save/restore ESP - slot 0, EAX - slot 1, EDX - slot 2, ECX - slot 3
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;
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%macro LOAD_ESP 0
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movd esp, xmm6
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%endmacro
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%macro SAVE_ESP 0
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SXMMN xmm6, 0, esp
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%endmacro
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%macro LOAD_EAX 0
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LXMMN xmm6, eax, 1
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%endmacro
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%macro SAVE_EAX 0
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SXMMN xmm6, 1, eax
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%endmacro
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%macro LOAD_EDX 0
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LXMMN xmm6, edx, 2
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%endmacro
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%macro SAVE_EDX 0
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SXMMN xmm6, 2, edx
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%endmacro
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%macro LOAD_ECX 0
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LXMMN xmm6, ecx, 3
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%endmacro
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%macro SAVE_ECX 0
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SXMMN xmm6, 3, ecx
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%endmacro
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;
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; XMM5 slot 0 for calling stack
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; arg 1:Entry
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%macro CALL_XMM 1
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mov esi, %%ReturnAddress
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SXMMN xmm5, 0, esi
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mov esi, %1
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jmp esi
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%%ReturnAddress:
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%endmacro
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%macro RET_XMM 0
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LXMMN xmm5, esi, 0
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jmp esi
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%endmacro
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;
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; XMM5 slot 1 for uCode status
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;
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%macro LOAD_UCODE_STATUS 0
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LXMMN xmm5, eax, 1
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%endmacro
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%macro SAVE_UCODE_STATUS 0
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SXMMN xmm5, 1, eax
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%endmacro
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;
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; XMM5 slot 2 for TemporaryRamSize
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;
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%macro LOAD_TEMPORARY_RAM_SIZE 1
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LXMMN xmm5, %1, 2
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%endmacro
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%macro SAVE_TEMPORARY_RAM_SIZE 1
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SXMMN xmm5, 2, %1
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%endmacro
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%macro ENABLE_SSE 0
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;
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; Initialize floating point units
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;
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jmp NextAddress
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align 4
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;
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; Float control word initial value:
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; all exceptions masked, double-precision, round-to-nearest
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;
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FpuControlWord DW 027Fh
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;
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; Multimedia-extensions control word:
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; all exceptions masked, round-to-nearest, flush to zero for masked underflow
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;
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MmxControlWord DD 01F80h
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SseError:
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;
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; Processor has to support SSE
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;
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jmp SseError
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NextAddress:
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finit
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fldcw [FpuControlWord]
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;
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; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
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; whether the processor supports SSE instruction.
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;
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; Save EBX to MM2
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;
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movd mm2, ebx
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mov eax, 1
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cpuid
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bt edx, 25
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jnc SseError
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%ifdef USE_SSE41_FLAG
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;
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; SSE 4.1 support
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;
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bt ecx, 19
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jnc SseError
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%endif
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;
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; Restore EBX from MM2
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;
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movd ebx, mm2
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;
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; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
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;
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mov eax, cr4
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or eax, 00000600h
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mov cr4, eax
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;
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; The processor should support SSE instruction and we can use
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; ldmxcsr instruction
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;
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ldmxcsr [MmxControlWord]
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%endmacro
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