43b7cd61c9
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
120 lines
3.2 KiB
C
120 lines
3.2 KiB
C
/** @file
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Copyright (C) 2016, Linaro Ltd. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available
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under the terms and conditions of the BSD License which accompanies this
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distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
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WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __NON_DISCOVERABLE_PCI_DEVICE_IO_H__
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#define __NON_DISCOVERABLE_PCI_DEVICE_IO_H__
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#include <PiDxe.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/UefiLib.h>
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#include <IndustryStandard/Pci.h>
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#include <Protocol/ComponentName.h>
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#include <Protocol/NonDiscoverableDevice.h>
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#include <Protocol/Cpu.h>
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#include <Protocol/PciIo.h>
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#define NON_DISCOVERABLE_PCI_DEVICE_SIG SIGNATURE_32 ('P', 'P', 'I', 'D')
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#define NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(PciIoPointer) \
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CR (PciIoPointer, NON_DISCOVERABLE_PCI_DEVICE, PciIo, \
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NON_DISCOVERABLE_PCI_DEVICE_SIG)
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#define PCI_ID_VENDOR_UNKNOWN 0xffff
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#define PCI_ID_DEVICE_DONTCARE 0x0000
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#define PCI_MAX_BARS 6
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extern EFI_CPU_ARCH_PROTOCOL *mCpu;
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typedef struct {
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//
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// The linked-list next pointer
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//
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LIST_ENTRY List;
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//
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// The address of the uncached allocation
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//
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VOID *HostAddress;
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//
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// The number of pages in the allocation
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//
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UINTN NumPages;
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//
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// The attributes of the allocation
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//
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UINT64 Attributes;
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} NON_DISCOVERABLE_DEVICE_UNCACHED_ALLOCATION;
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typedef struct {
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UINT32 Signature;
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//
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// The bound non-discoverable device protocol instance
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//
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NON_DISCOVERABLE_DEVICE *Device;
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//
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// The exposed PCI I/O protocol instance.
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//
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EFI_PCI_IO_PROTOCOL PciIo;
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//
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// The emulated PCI config space of the device. Only the minimally required
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// items are assigned.
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//
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PCI_TYPE00 ConfigSpace;
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//
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// The first virtual BAR to assign based on the resources described
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// by the non-discoverable device.
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//
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UINT32 BarOffset;
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//
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// The number of virtual BARs we expose based on the number of
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// resources
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//
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UINT32 BarCount;
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//
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// The PCI I/O attributes for this device
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//
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UINT64 Attributes;
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//
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// Whether this device has been enabled
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//
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BOOLEAN Enabled;
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//
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// Linked list to keep track of uncached allocations performed
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// on behalf of this device
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//
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LIST_ENTRY UncachedAllocationList;
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} NON_DISCOVERABLE_PCI_DEVICE;
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/**
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Initialize PciIo Protocol.
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@param Device Point to NON_DISCOVERABLE_PCI_DEVICE instance.
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**/
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VOID
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InitializePciIoProtocol (
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NON_DISCOVERABLE_PCI_DEVICE *Device
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);
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extern EFI_COMPONENT_NAME_PROTOCOL gComponentName;
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extern EFI_COMPONENT_NAME2_PROTOCOL gComponentName2;
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#endif
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