4059386c70
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
107 lines
2.3 KiB
ArmAsm
107 lines
2.3 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
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# Copyright (c) 2016, Linaro Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#------------------------------------------------------------------------------
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#include <AsmMacroIoLibV8.h>
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.set MPIDR_U_BIT, (30)
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.set MPIDR_U_MASK, (1 << MPIDR_U_BIT)
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// DAIF bit definitions for writing through msr daifclr/sr daifset
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.set DAIF_WR_FIQ_BIT, (1 << 0)
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.set DAIF_WR_IRQ_BIT, (1 << 1)
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.set DAIF_WR_ABORT_BIT, (1 << 2)
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.set DAIF_WR_DEBUG_BIT, (1 << 3)
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.set DAIF_WR_INT_BITS, (DAIF_WR_FIQ_BIT | DAIF_WR_IRQ_BIT)
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.set DAIF_WR_ALL, (DAIF_WR_DEBUG_BIT | DAIF_WR_ABORT_BIT | DAIF_WR_INT_BITS)
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ASM_FUNC(ArmIsMpCore)
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mrs x0, mpidr_el1 // Read EL1 Mutliprocessor Affinty Reg (MPIDR)
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and x0, x0, #MPIDR_U_MASK // U Bit clear, the processor is part of a multiprocessor system
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lsr x0, x0, #MPIDR_U_BIT
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eor x0, x0, #1
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ret
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ASM_FUNC(ArmEnableAsynchronousAbort)
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msr daifclr, #DAIF_WR_ABORT_BIT
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isb
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ret
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ASM_FUNC(ArmDisableAsynchronousAbort)
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msr daifset, #DAIF_WR_ABORT_BIT
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isb
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ret
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ASM_FUNC(ArmEnableIrq)
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msr daifclr, #DAIF_WR_IRQ_BIT
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isb
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ret
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ASM_FUNC(ArmDisableIrq)
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msr daifset, #DAIF_WR_IRQ_BIT
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isb
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ret
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ASM_FUNC(ArmEnableFiq)
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msr daifclr, #DAIF_WR_FIQ_BIT
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isb
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ret
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ASM_FUNC(ArmDisableFiq)
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msr daifset, #DAIF_WR_FIQ_BIT
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isb
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ret
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ASM_FUNC(ArmEnableInterrupts)
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msr daifclr, #DAIF_WR_INT_BITS
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isb
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ret
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ASM_FUNC(ArmDisableInterrupts)
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msr daifset, #DAIF_WR_INT_BITS
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isb
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ret
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ASM_FUNC(ArmDisableAllExceptions)
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msr daifset, #DAIF_WR_ALL
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isb
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ret
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// UINT32
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// ReadCCSIDR (
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// IN UINT32 CSSELR
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// )
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ASM_FUNC(ReadCCSIDR)
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msr csselr_el1, x0 // Write Cache Size Selection Register (CSSELR)
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isb
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mrs x0, ccsidr_el1 // Read current Cache Size ID Register (CCSIDR)
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ret
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// UINT32
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// ReadCLIDR (
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// IN UINT32 CSSELR
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// )
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ASM_FUNC(ReadCLIDR)
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mrs x0, clidr_el1 // Read Cache Level ID Register
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ret
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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