3cbfba02fe
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
374 lines
11 KiB
Plaintext
374 lines
11 KiB
Plaintext
/**************************************************************************;
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;* *;
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;* *;
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;* Intel Corporation - ACPI Reference Code for the Sandy Bridge *;
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;* Family of Customer Reference Boards. *;
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;* *;
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;* *;
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;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;
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;
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; This program and the accompanying materials are licensed and made available under
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; the terms and conditions of the BSD License that accompanies this distribution.
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; The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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;* *;
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;* *;
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;**************************************************************************/
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Scope(\_SB)
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{
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//RTC
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Device(RTC) // RTC
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{
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Name(_HID,EISAID("PNP0B00"))
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Name(_CRS,ResourceTemplate()
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{
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IO(Decode16,0x70,0x70,0x01,0x08)
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})
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}
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//RTC
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Device(HPET) // High Performance Event Timer
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{
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Name (_HID, EisaId ("PNP0103"))
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Name (_UID, 0x00)
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Method (_STA, 0, NotSerialized)
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{
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Return (0x0F)
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}
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Method (_CRS, 0, Serialized)
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{
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Name (RBUF, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite,
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0xFED00000, // Address Base
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0x00000400, // Address Length
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)
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Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
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{
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0x00000008, //0xB HPET-2
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}
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})
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Return (RBUF)
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}
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}
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//HPET
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Name(PR00, Package()
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{
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// SD Host #0 - eMMC
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Package() {0x0010FFFF, 0, LNKA, 0 },
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// SD Host #1 - SDIO
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Package() {0x0011FFFF, 0, LNKB, 0 },
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// SD Host #2 - SD Card
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Package() {0x0012FFFF, 0, LNKC, 0 },
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// SATA Controller
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Package() {0x0013FFFF, 0, LNKD, 0 },
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// xHCI Host
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Package() {0x0014FFFF, 0, LNKE, 0 },
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// Low Power Audio Engine
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Package() {0x0015FFFF, 0, LNKF, 0 },
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// USB OTG
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Package() {0x0016FFFF, 0, LNKG, 0 },
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// MIPI-HSI/eMMC4.5
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Package() {0x0017FFFF, 0, LNKH, 0 },
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// LPSS2 DMA
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// LPSS2 I2C #4
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Package() {0x0018FFFF, 0, LNKB, 0 },
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// LPSS2 I2C #1
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// LPSS2 I2C #5
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Package() {0x0018FFFF, 2, LNKD, 0 },
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// LPSS2 I2C #2
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// LPSS2 I2C #6
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Package() {0x0018FFFF, 3, LNKC, 0 },
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// LPSS2 I2C #3
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// LPSS2 I2C #7
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Package() {0x0018FFFF, 1, LNKA, 0 },
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// SeC
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Package() {0x001AFFFF, 0, LNKF, 0 },
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//
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// High Definition Audio Controller
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Package() {0x001BFFFF, 0, LNKG, 0 },
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//
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// EHCI Controller
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Package() {0x001DFFFF, 0, LNKH, 0 },
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// LPSS DMA
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Package() {0x001EFFFF, 0, LNKD, 0 },
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// LPSS I2C #0
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Package() {0x001EFFFF, 3, LNKA, 0 },
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// LPSS I2C #1
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Package() {0x001EFFFF, 1, LNKB, 0 },
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// LPSS PCM
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Package() {0x001EFFFF, 2, LNKC, 0 },
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// LPSS I2S
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// LPSS HS-UART #0
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// LPSS HS-UART #1
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// LPSS SPI
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// LPC Bridge
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//
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// SMBus Controller
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Package() {0x001FFFFF, 1, LNKC, 0 },
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//
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// PCIE Root Port #1
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Package() {0x001CFFFF, 0, LNKA, 0 },
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// PCIE Root Port #2
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Package() {0x001CFFFF, 1, LNKB, 0 },
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// PCIE Root Port #3
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Package() {0x001CFFFF, 2, LNKC, 0 },
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// PCIE Root Port #4
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Package() {0x001CFFFF, 3, LNKD, 0 },
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// Host Bridge
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// Mobile IGFX
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Package() {0x0002FFFF, 0, LNKA, 0 },
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})
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Name(AR00, Package()
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{
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// SD Host #0 - eMMC
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Package() {0x0010FFFF, 0, 0, 16 },
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// SD Host #1 - SDIO
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Package() {0x0011FFFF, 0, 0, 17 },
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// SD Host #2 - SD Card
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Package() {0x0012FFFF, 0, 0, 18 },
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// SATA Controller
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Package() {0x0013FFFF, 0, 0, 19 },
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// xHCI Host
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Package() {0x0014FFFF, 0, 0, 20 },
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// Low Power Audio Engine
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Package() {0x0015FFFF, 0, 0, 21 },
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// USB OTG
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Package() {0x0016FFFF, 0, 0, 22 },
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//
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// MIPI-HSI
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Package() {0x0017FFFF, 0, 0, 23 },
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//
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// LPSS2 DMA
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// LPSS2 I2C #4
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Package() {0x0018FFFF, 0, 0, 17 },
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// LPSS2 I2C #1
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// LPSS2 I2C #5
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Package() {0x0018FFFF, 2, 0, 19 },
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// LPSS2 I2C #2
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// LPSS2 I2C #6
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Package() {0x0018FFFF, 3, 0, 18 },
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// LPSS2 I2C #3
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// LPSS2 I2C #7
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Package() {0x0018FFFF, 1, 0, 16 },
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// SeC
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Package() {0x001AFFFF, 0, 0, 21 },
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//
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// High Definition Audio Controller
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Package() {0x001BFFFF, 0, 0, 22 },
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//
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// EHCI Controller
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Package() {0x001DFFFF, 0, 0, 23 },
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// LPSS DMA
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Package() {0x001EFFFF, 0, 0, 19 },
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// LPSS I2C #0
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Package() {0x001EFFFF, 3, 0, 16 },
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// LPSS I2C #1
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Package() {0x001EFFFF, 1, 0, 17 },
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// LPSS PCM
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Package() {0x001EFFFF, 2, 0, 18 },
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// LPSS I2S
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// LPSS HS-UART #0
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// LPSS HS-UART #1
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// LPSS SPI
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// LPC Bridge
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//
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// SMBus Controller
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Package() {0x001FFFFF, 1, 0, 18 },
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//
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// PCIE Root Port #1
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Package() {0x001CFFFF, 0, 0, 16 },
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// PCIE Root Port #2
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Package() {0x001CFFFF, 1, 0, 17 },
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// PCIE Root Port #3
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Package() {0x001CFFFF, 2, 0, 18 },
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// PCIE Root Port #4
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Package() {0x001CFFFF, 3, 0, 19 },
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// Host Bridge
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// Mobile IGFX
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Package() {0x0002FFFF, 0, 0, 16 },
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})
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Name(PR04, Package()
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{
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// PCIE Port #1 Slot
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Package() {0x0000FFFF, 0, LNKA, 0 },
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Package() {0x0000FFFF, 1, LNKB, 0 },
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Package() {0x0000FFFF, 2, LNKC, 0 },
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Package() {0x0000FFFF, 3, LNKD, 0 },
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})
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Name(AR04, Package()
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{
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// PCIE Port #1 Slot
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Package() {0x0000FFFF, 0, 0, 16 },
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Package() {0x0000FFFF, 1, 0, 17 },
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Package() {0x0000FFFF, 2, 0, 18 },
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Package() {0x0000FFFF, 3, 0, 19 },
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})
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Name(PR05, Package()
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{
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// PCIE Port #2 Slot
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Package() {0x0000FFFF, 0, LNKB, 0 },
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Package() {0x0000FFFF, 1, LNKC, 0 },
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Package() {0x0000FFFF, 2, LNKD, 0 },
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Package() {0x0000FFFF, 3, LNKA, 0 },
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})
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Name(AR05, Package()
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{
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// PCIE Port #2 Slot
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Package() {0x0000FFFF, 0, 0, 17 },
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Package() {0x0000FFFF, 1, 0, 18 },
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Package() {0x0000FFFF, 2, 0, 19 },
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Package() {0x0000FFFF, 3, 0, 16 },
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})
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Name(PR06, Package()
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{
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// PCIE Port #3 Slot
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Package() {0x0000FFFF, 0, LNKC, 0 },
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Package() {0x0000FFFF, 1, LNKD, 0 },
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Package() {0x0000FFFF, 2, LNKA, 0 },
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Package() {0x0000FFFF, 3, LNKB, 0 },
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})
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Name(AR06, Package()
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{
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// PCIE Port #3 Slot
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Package() {0x0000FFFF, 0, 0, 18 },
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Package() {0x0000FFFF, 1, 0, 19 },
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Package() {0x0000FFFF, 2, 0, 16 },
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Package() {0x0000FFFF, 3, 0, 17 },
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})
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Name(PR07, Package()
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{
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// PCIE Port #4 Slot
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Package() {0x0000FFFF, 0, LNKD, 0 },
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Package() {0x0000FFFF, 1, LNKA, 0 },
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Package() {0x0000FFFF, 2, LNKB, 0 },
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Package() {0x0000FFFF, 3, LNKC, 0 },
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})
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Name(AR07, Package()
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{
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// PCIE Port #4 Slot
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Package() {0x0000FFFF, 0, 0, 19 },
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Package() {0x0000FFFF, 1, 0, 16 },
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Package() {0x0000FFFF, 2, 0, 17 },
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Package() {0x0000FFFF, 3, 0, 18 },
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})
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Name(PR01, Package()
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{
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// PCI slot 1
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Package() {0x0000FFFF, 0, LNKF, 0 },
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Package() {0x0000FFFF, 1, LNKG, 0 },
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Package() {0x0000FFFF, 2, LNKH, 0 },
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Package() {0x0000FFFF, 3, LNKE, 0 },
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// PCI slot 2
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Package() {0x0001FFFF, 0, LNKG, 0 },
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Package() {0x0001FFFF, 1, LNKF, 0 },
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Package() {0x0001FFFF, 2, LNKE, 0 },
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Package() {0x0001FFFF, 3, LNKH, 0 },
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// PCI slot 3
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Package() {0x0002FFFF, 0, LNKC, 0 },
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Package() {0x0002FFFF, 1, LNKD, 0 },
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Package() {0x0002FFFF, 2, LNKB, 0 },
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Package() {0x0002FFFF, 3, LNKA, 0 },
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// PCI slot 4
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Package() {0x0003FFFF, 0, LNKD, 0 },
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Package() {0x0003FFFF, 1, LNKC, 0 },
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Package() {0x0003FFFF, 2, LNKF, 0 },
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Package() {0x0003FFFF, 3, LNKG, 0 },
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})
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Name(AR01, Package()
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{
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// PCI slot 1
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Package() {0x0000FFFF, 0, 0, 21 },
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Package() {0x0000FFFF, 1, 0, 22 },
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Package() {0x0000FFFF, 2, 0, 23 },
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Package() {0x0000FFFF, 3, 0, 20 },
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// PCI slot 2
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Package() {0x0001FFFF, 0, 0, 22 },
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Package() {0x0001FFFF, 1, 0, 21 },
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Package() {0x0001FFFF, 2, 0, 20 },
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Package() {0x0001FFFF, 3, 0, 23 },
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// PCI slot 3
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Package() {0x0002FFFF, 0, 0, 18 },
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Package() {0x0002FFFF, 1, 0, 19 },
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Package() {0x0002FFFF, 2, 0, 17 },
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Package() {0x0002FFFF, 3, 0, 16 },
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// PCI slot 4
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Package() {0x0003FFFF, 0, 0, 19 },
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Package() {0x0003FFFF, 1, 0, 18 },
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Package() {0x0003FFFF, 2, 0, 21 },
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Package() {0x0003FFFF, 3, 0, 22 },
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})
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//---------------------------------------------------------------------------
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// List of IRQ resource buffers compatible with _PRS return format.
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//---------------------------------------------------------------------------
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// Naming legend:
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// RSxy, PRSy - name of the IRQ resource buffer to be returned by _PRS, "xy" - last two characters of IRQ Link name.
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// Note. PRSy name is generated if IRQ Link name starts from "LNK".
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// HLxy , LLxy - reference names, can be used to access bit mask of available IRQs. HL and LL stand for active High(Low) Level triggered Irq model.
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//---------------------------------------------------------------------------
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Name(PRSA, ResourceTemplate() // Link name: LNKA
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{
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IRQ(Level, ActiveLow, Shared, LLKA) {3,4,5,6,10,11,12,14,15}
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})
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Alias(PRSA,PRSB) // Link name: LNKB
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Alias(PRSA,PRSC) // Link name: LNKC
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Alias(PRSA,PRSD) // Link name: LNKD
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Alias(PRSA,PRSE) // Link name: LNKE
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Alias(PRSA,PRSF) // Link name: LNKF
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Alias(PRSA,PRSG) // Link name: LNKG
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Alias(PRSA,PRSH) // Link name: LNKH
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//---------------------------------------------------------------------------
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// Begin PCI tree object scope
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//---------------------------------------------------------------------------
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Device(PCI0) // PCI Bridge "Host Bridge"
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{
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Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 host hierarchy
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Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't understand the new HID
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Name(_ADR, 0x00000000)
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Method(^BN00, 0) { return(0x0000) } // Returns default Bus number for Peer PCI busses. Name can be overriden with control method placed directly under Device scope
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Method(_BBN, 0) { return(BN00()) } // Bus number, optional for the Root PCI Bus
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Name(_UID, 0x0000) // Unique Bus ID, optional
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Name(_DEP, Package(0x1)
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{
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PEPD
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})
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Method(_PRT,0)
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{
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If(PICM) {Return(AR00)} // APIC mode
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Return (PR00) // PIC Mode
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} // end _PRT
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include("HOST_BUS.ASL")
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Device(LPCB) // LPC Bridge
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{
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Name(_ADR, 0x001F0000)
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include("LpcB.asl")
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} // end "LPC Bridge"
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} // end PCI0 Bridge "Host Bridge"
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} // end _SB scope
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