4a0f88dd64
On S3 path, we will wake up APs to restore CPU context in PiSmmCpuDxeSmm driver. However, we place AP in hlt-loop under 1MB space borrowed after CPU restoring CPU contexts. In case, one NMI or SMI happens, APs may exit from hlt state and execute the instruction after HLT instruction. But the code under 1MB is no longer safe at that time. This fix is to allocate one ACPI NVS range to place the AP hlt-loop code. When CPU finished restoration CPU contexts, AP will execute in this ACPI NVS range. https://bugzilla.tianocore.org/show_bug.cgi?id=216 v2: 1. Make stack alignment per Laszlo's comment. 2. Trim whitespace at end of end. 3. Update year mark in file header. Reported-by: Laszlo Ersek <lersek@redhat.com> Analyzed-by: Paolo Bonzini <pbonzini@redhat.com> Analyzed-by: Laszlo Ersek <lersek@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
122 lines
4.1 KiB
C
122 lines
4.1 KiB
C
/** @file
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SMM CPU misc functions for Ia32 arch specific.
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Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "PiSmmCpuDxeSmm.h"
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/**
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Initialize Gdt for all processors.
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@param[in] Cr3 CR3 value.
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@param[out] GdtStepSize The step size for GDT table.
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@return GdtBase for processor 0.
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GdtBase for processor X is: GdtBase + (GdtStepSize * X)
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**/
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VOID *
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InitGdt (
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IN UINTN Cr3,
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OUT UINTN *GdtStepSize
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)
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{
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UINTN Index;
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IA32_SEGMENT_DESCRIPTOR *GdtDescriptor;
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UINTN TssBase;
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UINTN GdtTssTableSize;
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UINT8 *GdtTssTables;
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UINTN GdtTableStepSize;
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if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
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//
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// For IA32 SMM, if SMM Stack Guard feature is enabled, we use 2 TSS.
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// in this case, we allocate separate GDT/TSS for each CPUs to avoid TSS load contention
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// on each SMI entry.
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//
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//
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// Enlarge GDT to contain 2 TSS descriptors
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//
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gcSmiGdtr.Limit += (UINT16)(2 * sizeof (IA32_SEGMENT_DESCRIPTOR));
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GdtTssTableSize = (gcSmiGdtr.Limit + 1 + TSS_SIZE * 2 + 7) & ~7; // 8 bytes aligned
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GdtTssTables = (UINT8*)AllocatePages (EFI_SIZE_TO_PAGES (GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus));
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ASSERT (GdtTssTables != NULL);
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GdtTableStepSize = GdtTssTableSize;
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for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {
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CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE * 2);
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//
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// Fixup TSS descriptors
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//
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TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1);
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GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2;
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GdtDescriptor->Bits.BaseLow = (UINT16)TssBase;
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GdtDescriptor->Bits.BaseMid = (UINT8)(TssBase >> 16);
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GdtDescriptor->Bits.BaseHigh = (UINT8)(TssBase >> 24);
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TssBase += TSS_SIZE;
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GdtDescriptor++;
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GdtDescriptor->Bits.BaseLow = (UINT16)TssBase;
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GdtDescriptor->Bits.BaseMid = (UINT8)(TssBase >> 16);
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GdtDescriptor->Bits.BaseHigh = (UINT8)(TssBase >> 24);
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//
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// Fixup TSS segments
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//
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// ESP as known good stack
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//
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*(UINTN *)(TssBase + TSS_IA32_ESP_OFFSET) = mSmmStackArrayBase + EFI_PAGE_SIZE + Index * mSmmStackSize;
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*(UINT32 *)(TssBase + TSS_IA32_CR3_OFFSET) = Cr3;
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}
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} else {
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//
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// Just use original table, AllocatePage and copy them here to make sure GDTs are covered in page memory.
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//
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GdtTssTableSize = gcSmiGdtr.Limit + 1;
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GdtTssTables = (UINT8*)AllocatePages (EFI_SIZE_TO_PAGES (GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus));
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ASSERT (GdtTssTables != NULL);
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GdtTableStepSize = GdtTssTableSize;
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for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {
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CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1);
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}
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}
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*GdtStepSize = GdtTableStepSize;
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return GdtTssTables;
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}
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/**
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Transfer AP to safe hlt-loop after it finished restore CPU features on S3 patch.
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@param[in] ApHltLoopCode The 32-bit address of the safe hlt-loop function.
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@param[in] TopOfStack A pointer to the new stack to use for the ApHltLoopCode.
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**/
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VOID
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TransferApToSafeState (
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IN UINT32 ApHltLoopCode,
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IN UINT32 TopOfStack
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)
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{
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SwitchStack (
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(SWITCH_STACK_ENTRY_POINT) (UINTN) ApHltLoopCode,
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NULL,
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NULL,
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(VOID *) (UINTN) TopOfStack
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);
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//
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// It should never reach here
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//
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ASSERT (FALSE);
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}
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