git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@3 6f19259b-4bc3-4df7-8a09-765794883524
		
			
				
	
	
		
			77 lines
		
	
	
		
			2.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			77 lines
		
	
	
		
			2.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*++
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| 
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| Copyright (c) 2006, Intel Corporation                                                         
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| All rights reserved. This program and the accompanying materials                          
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| are licensed and made available under the terms and conditions of the BSD License         
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| which accompanies this distribution.  The full text of the license may be found at        
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| http://opensource.org/licenses/bsd-license.php                                            
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|                                                                                           
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| THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
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| WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
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| 
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| Module Name:
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| 
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|     PeHotRelocateEx.h
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| 
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| Abstract:
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| 
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|     Fixes Intel Itanium(TM) specific relocation types
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| 
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| 
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| Revision History
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| 
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| --*/
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| 
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| #ifndef _PEHOTRELOCATE_EX_H_
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| #define _PEHOTRELOCATE_EX_H_
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| 
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| #define EXT_IMM64(Value, Address, Size, InstPos, ValPos) \
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|   Value |= (((UINT64) ((*(Address) >> InstPos) & (((UINT64) 1 << Size) - 1))) << ValPos)
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| 
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| #define INS_IMM64(Value, Address, Size, InstPos, ValPos) \
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|    * (UINT32 *) Address = \
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|     (*(UINT32 *) Address &~(((1 << Size) - 1) << InstPos)) | \
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|       ((UINT32) ((((UINT64) Value >> ValPos) & (((UINT64) 1 << Size) - 1))) << InstPos)
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| 
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| #define IMM64_IMM7B_INST_WORD_X       3
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| #define IMM64_IMM7B_SIZE_X            7
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| #define IMM64_IMM7B_INST_WORD_POS_X   4
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| #define IMM64_IMM7B_VAL_POS_X         0
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| 
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| #define IMM64_IMM9D_INST_WORD_X       3
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| #define IMM64_IMM9D_SIZE_X            9
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| #define IMM64_IMM9D_INST_WORD_POS_X   18
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| #define IMM64_IMM9D_VAL_POS_X         7
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| 
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| #define IMM64_IMM5C_INST_WORD_X       3
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| #define IMM64_IMM5C_SIZE_X            5
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| #define IMM64_IMM5C_INST_WORD_POS_X   13
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| #define IMM64_IMM5C_VAL_POS_X         16
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| 
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| #define IMM64_IC_INST_WORD_X          3
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| #define IMM64_IC_SIZE_X               1
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| #define IMM64_IC_INST_WORD_POS_X      12
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| #define IMM64_IC_VAL_POS_X            21
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| 
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| #define IMM64_IMM41a_INST_WORD_X      1
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| #define IMM64_IMM41a_SIZE_X           10
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| #define IMM64_IMM41a_INST_WORD_POS_X  14
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| #define IMM64_IMM41a_VAL_POS_X        22
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| 
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| #define IMM64_IMM41b_INST_WORD_X      1
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| #define IMM64_IMM41b_SIZE_X           8
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| #define IMM64_IMM41b_INST_WORD_POS_X  24
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| #define IMM64_IMM41b_VAL_POS_X        32
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| 
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| #define IMM64_IMM41c_INST_WORD_X      2
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| #define IMM64_IMM41c_SIZE_X           23
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| #define IMM64_IMM41c_INST_WORD_POS_X  0
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| #define IMM64_IMM41c_VAL_POS_X        40
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| 
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| #define IMM64_SIGN_INST_WORD_X        3
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| #define IMM64_SIGN_SIZE_X             1
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| #define IMM64_SIGN_INST_WORD_POS_X    27
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| #define IMM64_SIGN_VAL_POS_X          63
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| 
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| #endif
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