55a0d64b88
This library is the interface for the ARM Generic Interrupt Controller Architecture Specification. ARM Platform can use any GIC controller (not necessary PL390 GIC). git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12411 6f19259b-4bc3-4df7-8a09-765794883524
81 lines
3.0 KiB
C
81 lines
3.0 KiB
C
/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Uefi.h>
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#include <Library/IoLib.h>
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#include <Library/ArmGicLib.h>
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/*
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* This function configures the all interrupts to be Non-secure.
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*
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*/
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VOID
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EFIAPI
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ArmGicSetupNonSecure (
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IN INTN GicDistributorBase,
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IN INTN GicInterruptInterfaceBase
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)
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{
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UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
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// Set priority Mask so that no interrupts get through to CPU
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MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
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// Check if there are any pending interrupts
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//TODO: could be extended to take Peripheral interrupts into consideration, but at the moment only SGI's are taken into consideration.
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while(0 != (MmioRead32(GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {
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// Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
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UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
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// Write to End of interrupt signal
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MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
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}
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// Ensure all GIC interrupts are Non-Secure
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MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
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MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
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MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
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// Ensure all interrupts can get through the priority mask
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MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
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}
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VOID
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EFIAPI
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ArmGicEnableInterruptInterface (
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IN INTN GicInterruptInterfaceBase
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)
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{
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MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */
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/*
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* Enable CPU interface in Secure world
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* Enable CPU inteface in Non-secure World
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* Signal Secure Interrupts to CPU using FIQ line *
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*/
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MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCICR,
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ARM_GIC_ICCICR_ENABLE_SECURE |
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ARM_GIC_ICCICR_ENABLE_NS |
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ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);
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}
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VOID
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EFIAPI
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ArmGicEnableDistributor (
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IN INTN GicDistributorBase
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)
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{
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MmioWrite32(GicDistributorBase + ARM_GIC_ICDDCR, 1); // turn on the GIC distributor
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}
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