4f6d34b434
Move TimerDxe and ArmArchTimerLib to ArmGenericTimerCounterLib, and update all platforms to select the physical counter instance they have been using implicitly all along. Contributed-under: TianoCore Contribution Agreement 1.0 Acked-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16078 6f19259b-4bc3-4df7-8a09-765794883524
66 lines
1.8 KiB
C
66 lines
1.8 KiB
C
/** @file
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Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Base.h>
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#include <Library/ArmLib.h>
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#include <Library/ArmCpuLib.h>
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#include <Library/ArmGenericTimerCounterLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Chipset/ArmCortexA15.h>
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VOID
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ArmCpuSetup (
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IN UINTN MpId
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)
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{
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// Check if Architectural Timer frequency is valid number (should not be 0)
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ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));
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ASSERT(ArmIsArchTimerImplemented () != 0);
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// Enable SWP instructions
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ArmEnableSWPInstruction ();
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// Enable program flow prediction, if supported.
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ArmEnableBranchPrediction ();
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// Note: System Counter frequency can only be set in Secure privileged mode,
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// if security extensions are implemented.
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ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
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if (ArmIsMpCore()) {
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// Turn on SMP coherency
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ArmSetAuxCrBit (A15_FEATURE_SMP);
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}
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}
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VOID
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ArmCpuSetupSmpNonSecure (
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IN UINTN MpId
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)
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{
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/*// Make the SCU accessible in Non Secure world
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if (ArmPlatformIsPrimaryCore (MpId)) {
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ScuBase = ArmGetScuBaseAddress();
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// Allow NS access to SCU register
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MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);
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// Allow NS access to Private Peripherals
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MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);
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}*/
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}
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