37ec4d9af7
Even if the CPU id registers indicate hardware support for the System Register interface to the GIC, higher exception levels may disable that interface and only allow access through MMIO. So move the enabling of the SRE bit to the GIC version detection routine: if we trigger an exception, we would have anyway at a later stage, so the net effect is the same. However, if setting the bit doesn't stick, it means we can switch to MMIO and proceed normally otherwise. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16344 6f19259b-4bc3-4df7-8a09-765794883524
48 lines
1.8 KiB
C
48 lines
1.8 KiB
C
/** @file
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*
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* Copyright (c) 2014, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials are licensed and made available
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* under the terms and conditions of the BSD License which accompanies this
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* distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Library/ArmLib.h>
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#include <Library/ArmGicLib.h>
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#include "GicV3/ArmGicV3Lib.h"
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ARM_GIC_ARCH_REVISION
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EFIAPI
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ArmGicGetSupportedArchRevision (
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VOID
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)
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{
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// Ideally we would like to use the GICC IIDR Architecture version here, but
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// this does not seem to be very reliable as the implementation could easily
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// get it wrong. It is more reliable to check if the GICv3 System Register
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// feature is implemented on the CPU. This is also convenient as our GICv3
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// driver requires SRE. If only Memory mapped access is available we try to
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// drive the GIC as a v2.
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if (ArmReadIdPfr1 () & ARM_PFR1_GIC) {
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// Make sure System Register access is enabled (SRE). This depends on the
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// higher privilege level giving us permission, otherwise we will either
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// cause an exception here, or the write doesn't stick in which case we need
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// to fall back to the GICv2 MMIO interface.
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// Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started
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// at the same exception level.
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// It is the OS responsibility to set this bit.
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ArmGicV3SetControlSystemRegisterEnable (ArmGicV3GetControlSystemRegisterEnable () | ICC_SRE_EL2_SRE);
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if (ArmGicV3GetControlSystemRegisterEnable () & ICC_SRE_EL2_SRE) {
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return ARM_GIC_ARCH_REVISION_3;
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}
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}
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return ARM_GIC_ARCH_REVISION_2;
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}
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