793ca69f50
The support for GIcV2 was already existing. This change separate the GicV2 specific functions from the common Gic code (in preparation for GicV3 support). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15626 6f19259b-4bc3-4df7-8a09-765794883524
101 lines
3.3 KiB
C
101 lines
3.3 KiB
C
/** @file
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*
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* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Base.h>
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#include <Library/ArmLib.h>
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#include <Library/ArmPlatformLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/ArmGicLib.h>
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/*
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* This function configures the all interrupts to be Non-secure.
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*
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*/
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VOID
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EFIAPI
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ArmGicV2SetupNonSecure (
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IN UINTN MpId,
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IN INTN GicDistributorBase,
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IN INTN GicInterruptInterfaceBase
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)
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{
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UINTN InterruptId;
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UINTN CachedPriorityMask;
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UINTN Index;
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UINTN MaxInterrupts;
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CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
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// Set priority Mask so that no interrupts get through to CPU
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
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InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
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MaxInterrupts = ArmGicGetMaxNumInterrupts (GicDistributorBase);
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// Only try to clear valid interrupts. Ignore spurious interrupts.
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while ((InterruptId & 0x3FF) < MaxInterrupts) {
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// Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
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ArmGicEndOfInterrupt (GicInterruptInterfaceBase, InterruptId);
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// Next
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InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
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}
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// Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).
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if (ArmPlatformIsPrimaryCore (MpId)) {
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// Ensure all GIC interrupts are Non-Secure
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for (Index = 0; Index < (MaxInterrupts / 32); Index++) {
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MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);
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}
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} else {
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// The secondary cores only set the Non Secure bit to their banked PPIs
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MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);
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}
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// Ensure all interrupts can get through the priority mask
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
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}
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VOID
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EFIAPI
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ArmGicV2EnableInterruptInterface (
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IN INTN GicInterruptInterfaceBase
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)
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{
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// Set Priority Mask to allow interrupts
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);
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// Enable CPU interface in Secure world
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// Enable CPU interface in Non-secure World
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// Signal Secure Interrupts to CPU using FIQ line *
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,
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ARM_GIC_ICCICR_ENABLE_SECURE |
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ARM_GIC_ICCICR_ENABLE_NS |
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ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);
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}
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VOID
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EFIAPI
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ArmGicV2DisableInterruptInterface (
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IN INTN GicInterruptInterfaceBase
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)
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{
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UINT32 ControlValue;
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// Disable CPU interface in Secure world and Non-secure World
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ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR);
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS));
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}
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