01674afdad
Cache maintenance operations by Set/Way require that the Write Buffer be drained before the cache is flushed. Without that, the flush can miss the most recent values written as they are still "pipelined". That has unfortunate consequences, especially where code is being copied to RAM. The fix is to add DSB instructions before the affected operations. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15551 6f19259b-4bc3-4df7-8a09-765794883524
268 lines
4.6 KiB
C
268 lines
4.6 KiB
C
/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Uefi.h>
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#include <Chipset/AArch64.h>
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#include <Library/ArmLib.h>
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#include <Library/BaseLib.h>
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#include <Library/IoLib.h>
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#include "AArch64Lib.h"
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#include "ArmLibPrivate.h"
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ARM_CACHE_TYPE
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EFIAPI
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ArmCacheType (
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VOID
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)
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{
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return ARM_CACHE_TYPE_WRITE_BACK;
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}
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ARM_CACHE_ARCHITECTURE
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EFIAPI
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ArmCacheArchitecture (
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VOID
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)
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{
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UINT32 CLIDR = ReadCLIDR ();
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return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me
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}
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BOOLEAN
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EFIAPI
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ArmDataCachePresent (
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VOID
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)
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{
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UINT32 CLIDR = ReadCLIDR ();
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if ((CLIDR & 0x2) == 0x2) {
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// Instruction cache exists
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return TRUE;
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}
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if ((CLIDR & 0x7) == 0x4) {
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// Unified cache
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return TRUE;
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}
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return FALSE;
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}
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UINTN
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EFIAPI
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ArmDataCacheSize (
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VOID
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)
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{
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UINT32 NumSets;
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UINT32 Associativity;
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UINT32 LineSize;
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UINT32 CCSIDR = ReadCCSIDR (0);
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LineSize = (1 << ((CCSIDR & 0x7) + 2));
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Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
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NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
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// LineSize is in words (4 byte chunks)
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return NumSets * Associativity * LineSize * 4;
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}
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UINTN
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EFIAPI
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ArmDataCacheAssociativity (
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VOID
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)
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{
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UINT32 CCSIDR = ReadCCSIDR (0);
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return ((CCSIDR >> 3) & 0x3ff) + 1;
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}
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UINTN
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ArmDataCacheSets (
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VOID
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)
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{
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UINT32 CCSIDR = ReadCCSIDR (0);
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return ((CCSIDR >> 13) & 0x7fff) + 1;
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}
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UINTN
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EFIAPI
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ArmDataCacheLineLength (
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VOID
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)
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{
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UINT32 CCSIDR = ReadCCSIDR (0) & 7;
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// * 4 converts to bytes
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return (1 << (CCSIDR + 2)) * 4;
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}
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BOOLEAN
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EFIAPI
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ArmInstructionCachePresent (
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VOID
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)
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{
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UINT32 CLIDR = ReadCLIDR ();
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if ((CLIDR & 1) == 1) {
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// Instruction cache exists
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return TRUE;
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}
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if ((CLIDR & 0x7) == 0x4) {
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// Unified cache
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return TRUE;
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}
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return FALSE;
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}
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UINTN
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EFIAPI
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ArmInstructionCacheSize (
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VOID
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)
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{
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UINT32 NumSets;
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UINT32 Associativity;
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UINT32 LineSize;
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UINT32 CCSIDR = ReadCCSIDR (1);
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LineSize = (1 << ((CCSIDR & 0x7) + 2));
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Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
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NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
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// LineSize is in words (4 byte chunks)
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return NumSets * Associativity * LineSize * 4;
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}
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UINTN
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EFIAPI
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ArmInstructionCacheAssociativity (
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VOID
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)
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{
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UINT32 CCSIDR = ReadCCSIDR (1);
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return ((CCSIDR >> 3) & 0x3ff) + 1;
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}
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UINTN
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EFIAPI
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ArmInstructionCacheSets (
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VOID
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)
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{
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UINT32 CCSIDR = ReadCCSIDR (1);
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return ((CCSIDR >> 13) & 0x7fff) + 1;
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}
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UINTN
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EFIAPI
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ArmInstructionCacheLineLength (
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VOID
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)
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{
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UINT32 CCSIDR = ReadCCSIDR (1) & 7;
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// * 4 converts to bytes
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return (1 << (CCSIDR + 2)) * 4;
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}
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VOID
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AArch64DataCacheOperation (
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IN AARCH64_CACHE_OPERATION DataCacheOperation
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)
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{
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UINTN SavedInterruptState;
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SavedInterruptState = ArmGetInterruptState ();
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ArmDisableInterrupts();
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AArch64AllDataCachesOperation (DataCacheOperation);
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ArmDrainWriteBuffer ();
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if (SavedInterruptState) {
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ArmEnableInterrupts ();
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}
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}
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VOID
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AArch64PoUDataCacheOperation (
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IN AARCH64_CACHE_OPERATION DataCacheOperation
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)
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{
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UINTN SavedInterruptState;
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SavedInterruptState = ArmGetInterruptState ();
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ArmDisableInterrupts ();
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AArch64PerformPoUDataCacheOperation (DataCacheOperation);
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ArmDrainWriteBuffer ();
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if (SavedInterruptState) {
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ArmEnableInterrupts ();
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}
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}
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VOID
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EFIAPI
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ArmInvalidateDataCache (
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VOID
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)
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{
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ArmDrainWriteBuffer ();
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AArch64DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
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}
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VOID
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EFIAPI
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ArmCleanInvalidateDataCache (
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VOID
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)
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{
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ArmDrainWriteBuffer ();
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AArch64DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
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}
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VOID
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EFIAPI
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ArmCleanDataCache (
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VOID
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)
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{
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ArmDrainWriteBuffer ();
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AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
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}
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VOID
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EFIAPI
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ArmCleanDataCacheToPoU (
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VOID
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)
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{
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ArmDrainWriteBuffer ();
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AArch64PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);
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}
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