fb7ea6114a
From the AArch64 Procedure Call Standard (ARM IHI 0055B): 5.2.2.1 Universal stack constraints At all times the following basic constraints must hold: - SP mod 16 = 0. The stack must be quad-word aligned. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16327 6f19259b-4bc3-4df7-8a09-765794883524
42 lines
1.2 KiB
ArmAsm
42 lines
1.2 KiB
ArmAsm
//
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// Copyright (c) 2012-2014, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//
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.text
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.align 3
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GCC_ASM_EXPORT(ArmCallSmc)
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ASM_PFX(ArmCallSmc):
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// Push x0 on the stack - The stack must always be quad-word aligned
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str x0, [sp, #-16]!
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// Load the SMC arguments values into the appropriate registers
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ldp x6, x7, [x0, #48]
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ldp x4, x5, [x0, #32]
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ldp x2, x3, [x0, #16]
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ldp x0, x1, [x0, #0]
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smc #0
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// Pop the ARM_SMC_ARGS structure address from the stack into x9
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ldr x9, [sp], #16
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// Store the SMC returned values into the ARM_SMC_ARGS structure.
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// A SMC call can return up to 4 values - we do not need to store back x4-x7.
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stp x2, x3, [x9, #16]
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stp x0, x1, [x9, #0]
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mov x0, x9
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ret
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