5cc25cff5d
Create a helper function to eliminate direct feature register reading, which gets messy in code shared between ARM/AArch64. Returns BOOLEAN True if the CPU implements the GIC System Register Interface (any version), otherwise returns BOOL False. Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Signed-off-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
90 lines
1.7 KiB
C
90 lines
1.7 KiB
C
/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
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Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Library/ArmLib.h>
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#include <Library/DebugLib.h>
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#include <Chipset/AArch64.h>
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#include "AArch64Lib.h"
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#include "ArmLibPrivate.h"
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VOID
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AArch64DataCacheOperation (
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IN AARCH64_CACHE_OPERATION DataCacheOperation
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)
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{
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UINTN SavedInterruptState;
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SavedInterruptState = ArmGetInterruptState ();
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ArmDisableInterrupts();
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AArch64AllDataCachesOperation (DataCacheOperation);
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ArmDataSynchronizationBarrier ();
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if (SavedInterruptState) {
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ArmEnableInterrupts ();
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}
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}
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VOID
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EFIAPI
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ArmInvalidateDataCache (
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VOID
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)
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{
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ASSERT (!ArmMmuEnabled ());
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ArmDataSynchronizationBarrier ();
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AArch64DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
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}
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VOID
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EFIAPI
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ArmCleanInvalidateDataCache (
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VOID
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)
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{
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ASSERT (!ArmMmuEnabled ());
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ArmDataSynchronizationBarrier ();
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AArch64DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
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}
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VOID
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EFIAPI
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ArmCleanDataCache (
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VOID
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)
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{
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ASSERT (!ArmMmuEnabled ());
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ArmDataSynchronizationBarrier ();
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AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
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}
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/**
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Check whether the CPU supports the GIC system register interface (any version)
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@return Whether GIC System Register Interface is supported
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**/
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BOOLEAN
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EFIAPI
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ArmHasGicSystemRegisters (
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VOID
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)
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{
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return ((ArmReadIdPfr0 () & AARCH64_PFR0_GIC) != 0);
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}
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