system76-edk2/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt2.0.aslc

/** @file
This file describes the contents of the ACPI Fixed ACPI Description Table
(FADT).  Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h.
All changes to the FADT contents should be done in this file.

Copyright (c) 2013-2015 Intel Corporation.

SPDX-License-Identifier: BSD-2-Clause-Patent

**/

#include "Fadt.h"

EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE FADT = {
  {
    EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
    sizeof (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE),
    EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
    0,                    // to make sum of entire table == 0
    {EFI_ACPI_OEM_ID},    // OEMID is a 6 bytes long field
    EFI_ACPI_OEM_TABLE_ID,// OEM table identification(8 bytes long)
    EFI_ACPI_OEM_REVISION,// OEM revision number
    EFI_ACPI_CREATOR_ID,  // ASL compiler vendor ID
    EFI_ACPI_CREATOR_REVISION  // ASL compiler revision number
  },
  0,                    // Physical addesss of FACS
  0,                    // Physical address of DSDT
  RESERVED,             // reserved
  PM_PROFILE,           // Preferred powermanagement profile
  SCI_INT_VECTOR,       // System vector of SCI interrupt
  ACPI_RUNTIME_UPDATE,  // Port address of SMI command port
  ACPI_ENABLE,          // value to write to port smi_cmd to enable ACPI
  ACPI_DISABLE,         // value to write to port smi_cmd to disable ACPI
  S4BIOS_REQ,           // Value to write to SMI CMD port to enter the S4BIOS state
  RESERVED,             // reserved - must be zero
  ACPI_RUNTIME_UPDATE,  // Port address of Power Mgt 1a Event Reg Blk
  PM1b_EVT_BLK_ADDRESS, // Port address of Power Mgt 1b Event Reg Blk
  ACPI_RUNTIME_UPDATE,  // Port address of Power Mgt 1a Ctrl Reg Blk
  PM1b_CNT_BLK_ADDRESS, // Port address of Power Mgt 1b Ctrl Reg Blk
  ACPI_RUNTIME_UPDATE,  // Port address of Power Mgt 2  Ctrl Reg Blk
  ACPI_RUNTIME_UPDATE,  // Port address of Power Mgt Timer Ctrl Reg Blk
  ACPI_RUNTIME_UPDATE,  // Port addr of General Purpose Event 0 Reg Blk
  GPE1_BLK_ADDRESS,     // Port addr of General Purpose Event 1 Reg Blk
  PM1_EVT_LEN,          // Byte Length of ports at pm1X_evt_blk
  PM1_CNT_LEN,          // Byte Length of ports at pm1X_cnt_blk
  PM2_CNT_LEN,          // Byte Length of ports at pm2_cnt_blk
  PM_TM_LEN,            // Byte Length of ports at pm_tm_blk
  GPE0_BLK_LEN,         // Byte Length of ports at gpe0_blk
  GPE1_BLK_LEN,         // Byte Length of ports at gpe1_blk
  GPE1_BASE,            // offset in gpe model where gpe1 events start
  RESERVED,             // reserved
  P_LVL2_LAT,           // worst case HW latency to enter/exit C2 state
  P_LVL3_LAT,           // worst case HW latency to enter/exit C3 state
  FLUSH_SIZE,           // Size of area read to flush caches
  FLUSH_STRIDE,         // Stride used in flushing caches
  DUTY_OFFSET,          // bit location of duty cycle field in p_cnt reg
  DUTY_WIDTH,           // bit width of duty cycle field in p_cnt reg
  DAY_ALRM,             // index to day-of-month alarm in RTC CMOS RAM
  MON_ALRM,             // index to month-of-year alarm in RTC CMOS RAM
  CENTURY,              // index to century in RTC CMOS RAM
  IAPC_BOOT_ARCH,       // IA-PC Boot Architecture Flags
  RESERVED,             // reserved
  FLAG2,                // Fixed feature flags

  {
    RESET_REG_ADDRESS_SPACE_ID,  // Address of the reset register
    RESET_REG_BIT_WIDTH,
    RESET_REG_BIT_OFFSET,
    RESERVED,
    RESET_REG_ADDRESS
  },
  RESET_VALUE,          // Value to write to the RESET_REG port
  {
    RESERVED,
    RESERVED,
    RESERVED
  },
  0,                // 64Bit physical addesss of FACS
  0,                // 64Bit physical address of DSDT

  {
    PM1a_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1a Event Reg Blk
    PM1a_EVT_BLK_BIT_WIDTH,
    PM1a_EVT_BLK_BIT_OFFSET,
    RESERVED,
    ACPI_RUNTIME_UPDATE
  },

  {
    PM1b_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1b Event Reg Blk
    PM1b_EVT_BLK_BIT_WIDTH,
    PM1b_EVT_BLK_BIT_OFFSET,
    RESERVED,
    PM1b_EVT_BLK_ADDRESS
  },

  {
    PM1a_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1a Ctrl Reg Blk
    PM1a_CNT_BLK_BIT_WIDTH,
    PM1a_CNT_BLK_BIT_OFFSET,
    RESERVED,
    ACPI_RUNTIME_UPDATE
  },

  {
    PM1b_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1b Ctrl Reg Blk
    PM1b_CNT_BLK_BIT_WIDTH,
    PM1b_CNT_BLK_BIT_OFFSET,
    RESERVED,
    PM1b_CNT_BLK_ADDRESS
  },

  {
    PM2_CNT_BLK_ADDRESS_SPACE_ID,  // Extended Port address of Power Mgt 2  Ctrl Reg Blk
    PM2_CNT_BLK_BIT_WIDTH,
    PM2_CNT_BLK_BIT_OFFSET,
    RESERVED,
    ACPI_RUNTIME_UPDATE
  },

  {
    PM_TMR_BLK_ADDRESS_SPACE_ID,   // Extended Port address of Power Mgt Timer Ctrl Reg Blk
    PM_TMR_BLK_BIT_WIDTH,
    PM_TMR_BLK_BIT_OFFSET,
    RESERVED,
    ACPI_RUNTIME_UPDATE
  },

  {
    GPE0_BLK_ADDRESS_SPACE_ID,   // Extended Port address of General Purpose Event 0 Reg Blk
    GPE0_BLK_BIT_WIDTH,
    GPE0_BLK_BIT_OFFSET,
    RESERVED,
    ACPI_RUNTIME_UPDATE
  },

  {
    GPE1_BLK_ADDRESS_SPACE_ID,   // Extended Port address of General Purpose Event 1 Reg Blk
    GPE1_BLK_BIT_WIDTH,
    GPE1_BLK_BIT_OFFSET,
    RESERVED,
    GPE1_BLK_ADDRESS
  }
};

VOID*
ReferenceAcpiTable (
  VOID
  )

{
  //
  // Reference the table being generated to prevent the optimizer from removing the
  // data structure from the exeutable
  //
  return (VOID*)&FADT;
}