0eb3de2edc
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
444 lines
11 KiB
C
444 lines
11 KiB
C
/** @file
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Essential platform configuration.
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Copyright (c) 2013 Intel Corporation.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PlatformInitDxe.h"
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//
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// The protocols, PPI and GUID defintions for this module
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//
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//
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// The Library classes this module consumes
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//
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//
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// RTC:28208 - System hang/crash when entering probe mode(ITP) when relocating SMBASE
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// Workaround to make default SMRAM UnCachable
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//
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#define SMM_DEFAULT_SMBASE 0x30000 // Default SMBASE address
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#define SMM_DEFAULT_SMBASE_SIZE_BYTES 0x10000 // Size in bytes of default SMRAM
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BOOLEAN mMemCfgDone = FALSE;
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UINT8 ChipsetDefaultMac [6] = {0xff,0xff,0xff,0xff,0xff,0xff};
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VOID
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EFIAPI
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PlatformInitializeUart0MuxGalileo (
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VOID
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)
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/*++
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Routine Description:
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This is the routine to initialize UART0 for DBG2 support. The hardware used in this process is a
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Legacy Bridge (Legacy GPIO), I2C controller, a bi-directional MUX and a Cypress CY8C9540A chip.
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Arguments:
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None.
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Returns:
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None.
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--*/
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{
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EFI_STATUS Status;
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EFI_I2C_DEVICE_ADDRESS I2CSlaveAddress;
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UINTN Length;
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UINT8 Buffer[2];
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if (PlatformLegacyGpioGetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)) {
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I2CSlaveAddress.I2CDeviceAddress = GALILEO_IOEXP_J2HI_7BIT_SLAVE_ADDR;
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} else {
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I2CSlaveAddress.I2CDeviceAddress = GALILEO_IOEXP_J2LO_7BIT_SLAVE_ADDR;
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}
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//
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// Set GPIO_SUS<2> as an output, raise voltage to Vdd.
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//
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PlatformLegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, 2, TRUE);
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//
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// Select Port 3
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//
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Length = 2;
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Buffer[0] = 0x18; //sub-address
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Buffer[1] = 0x03; //data
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Status = I2cWriteMultipleByte (
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I2CSlaveAddress,
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EfiI2CSevenBitAddrMode,
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&Length,
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&Buffer
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);
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ASSERT_EFI_ERROR (Status);
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//
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// Set "Pin Direction" bit4 and bit5 as outputs
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//
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Length = 2;
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Buffer[0] = 0x1C; //sub-address
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Buffer[1] = 0xCF; //data
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Status = I2cWriteMultipleByte (
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I2CSlaveAddress,
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EfiI2CSevenBitAddrMode,
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&Length,
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&Buffer
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);
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ASSERT_EFI_ERROR (Status);
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//
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// Lower GPORT3 bit4 and bit5 to Vss
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//
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Length = 2;
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Buffer[0] = 0x0B; //sub-address
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Buffer[1] = 0xCF; //data
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Status = I2cWriteMultipleByte (
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I2CSlaveAddress,
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EfiI2CSevenBitAddrMode,
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&Length,
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&Buffer
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);
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ASSERT_EFI_ERROR (Status);
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}
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VOID
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EFIAPI
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PlatformInitializeUart0MuxGalileoGen2 (
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VOID
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)
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/*++
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Routine Description:
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This is the routine to initialize UART0 on GalileoGen2. The hardware used in this process is
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I2C controller and the configuring the following IO Expander signal.
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EXP1.P1_5 should be configured as an output & driven high.
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EXP1.P0_0 should be configured as an output & driven high.
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EXP0.P1_4 should be configured as an output, driven low.
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EXP1.P0_1 pullup should be disabled.
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EXP0.P1_5 Pullup should be disabled.
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Arguments:
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None.
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Returns:
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None.
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--*/
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{
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//
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// EXP1.P1_5 should be configured as an output & driven high.
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//
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PlatformPcal9555GpioSetDir (
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GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1.
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13, // P1-5.
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TRUE
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);
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PlatformPcal9555GpioSetLevel (
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GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1.
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13, // P1-5.
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TRUE
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);
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//
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// EXP1.P0_0 should be configured as an output & driven high.
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//
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PlatformPcal9555GpioSetDir (
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GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.
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0, // P0_0.
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TRUE
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);
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PlatformPcal9555GpioSetLevel (
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GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.
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0, // P0_0.
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TRUE
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);
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//
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// EXP0.P1_4 should be configured as an output, driven low.
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//
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PlatformPcal9555GpioSetDir (
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GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.
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12, // P1-4.
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FALSE
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);
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PlatformPcal9555GpioSetLevel ( // IO Expander 0.
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GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // P1-4
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12,
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FALSE
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);
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//
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// EXP1.P0_1 pullup should be disabled.
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//
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PlatformPcal9555GpioDisablePull (
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GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1.
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1 // P0-1.
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);
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//
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// EXP0.P1_5 Pullup should be disabled.
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//
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PlatformPcal9555GpioDisablePull (
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GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.
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13 // P1-5.
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);
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}
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VOID
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EFIAPI
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PlatformConfigOnSmmConfigurationProtocol (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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/*++
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Routine Description:
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Function runs in PI-DXE to perform platform specific config when
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SmmConfigurationProtocol is installed.
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Arguments:
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Event - The event that occured.
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Context - For EFI compatiblity. Not used.
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Returns:
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None.
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--*/
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{
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EFI_STATUS Status;
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UINT32 NewValue;
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UINT64 BaseAddress;
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UINT64 SmramLength;
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VOID *SmmCfgProt;
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Status = gBS->LocateProtocol (&gEfiSmmConfigurationProtocolGuid, NULL, &SmmCfgProt);
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if (Status != EFI_SUCCESS){
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DEBUG ((DEBUG_INFO, "gEfiSmmConfigurationProtocolGuid triggered but not valid.\n"));
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return;
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}
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if (mMemCfgDone) {
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DEBUG ((DEBUG_INFO, "Platform DXE Mem config already done.\n"));
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return;
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}
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//
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// Disable eSram block (this will also clear/zero eSRAM)
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// We only use eSRAM in the PEI phase. Disable now that we are in the DXE phase
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//
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NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK);
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NewValue |= BLOCK_DISABLE_PG;
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QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK, NewValue);
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//
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// Update HMBOUND to top of DDR3 memory and LOCK
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// We disabled eSRAM so now we move HMBOUND down to top of DDR3
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//
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QNCGetTSEGMemoryRange (&BaseAddress, &SmramLength);
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NewValue = (UINT32)(BaseAddress + SmramLength);
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DEBUG ((EFI_D_INFO,"Locking HMBOUND at: = 0x%8x\n",NewValue));
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QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_HMBOUND_REG, (NewValue | HMBOUND_LOCK));
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//
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// Lock IMR5 now that HMBOUND is locked (legacy S3 region)
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//
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NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR5+QUARK_NC_MEMORY_MANAGER_IMRXL);
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NewValue |= IMR_LOCK;
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QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR5+QUARK_NC_MEMORY_MANAGER_IMRXL, NewValue);
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//
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// Lock IMR6 now that HMBOUND is locked (ACPI Reclaim/ACPI/Runtime services/Reserved)
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//
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NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR6+QUARK_NC_MEMORY_MANAGER_IMRXL);
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NewValue |= IMR_LOCK;
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QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR6+QUARK_NC_MEMORY_MANAGER_IMRXL, NewValue);
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//
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// Disable IMR2 memory protection (RMU Main Binary)
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//
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QncImrWrite (
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QUARK_NC_MEMORY_MANAGER_IMR2,
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(UINT32)(IMRL_RESET & ~IMR_EN),
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(UINT32)IMRH_RESET,
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(UINT32)IMRX_ALL_ACCESS,
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(UINT32)IMRX_ALL_ACCESS
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);
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//
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// Disable IMR3 memory protection (Default SMRAM)
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//
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QncImrWrite (
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QUARK_NC_MEMORY_MANAGER_IMR3,
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(UINT32)(IMRL_RESET & ~IMR_EN),
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(UINT32)IMRH_RESET,
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(UINT32)IMRX_ALL_ACCESS,
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(UINT32)IMRX_ALL_ACCESS
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);
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//
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// Disable IMR4 memory protection (eSRAM).
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//
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QncImrWrite (
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QUARK_NC_MEMORY_MANAGER_IMR4,
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(UINT32)(IMRL_RESET & ~IMR_EN),
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(UINT32)IMRH_RESET,
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(UINT32)IMRX_ALL_ACCESS,
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(UINT32)IMRX_ALL_ACCESS
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);
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//
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// RTC:28208 - System hang/crash when entering probe mode(ITP) when relocating SMBASE
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// Workaround to make default SMRAM UnCachable
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//
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Status = gDS->SetMemorySpaceAttributes (
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(EFI_PHYSICAL_ADDRESS) SMM_DEFAULT_SMBASE,
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SMM_DEFAULT_SMBASE_SIZE_BYTES,
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EFI_MEMORY_WB
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);
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ASSERT_EFI_ERROR (Status);
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mMemCfgDone = TRUE;
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}
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VOID
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EFIAPI
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PlatformConfigOnSpiReady (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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/*++
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Routine Description:
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Function runs in PI-DXE to perform platform specific config when SPI
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interface is ready.
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Arguments:
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Event - The event that occured.
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Context - For EFI compatiblity. Not used.
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Returns:
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None.
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--*/
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{
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EFI_STATUS Status;
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VOID *SpiReadyProt = NULL;
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EFI_PLATFORM_TYPE Type;
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EFI_BOOT_MODE BootMode;
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BootMode = GetBootModeHob ();
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Status = gBS->LocateProtocol (&gEfiSmmSpiReadyProtocolGuid, NULL, &SpiReadyProt);
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if (Status != EFI_SUCCESS){
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DEBUG ((DEBUG_INFO, "gEfiSmmSpiReadyProtocolGuid triggered but not valid.\n"));
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return;
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}
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//
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// Lock regions SPI flash.
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//
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PlatformFlashLockPolicy (FALSE);
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//
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// Configurations and checks to be done when DXE tracing available.
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//
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//
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// Platform specific Signal routing.
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//
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//
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// Skip any signal not needed for recovery and flash update.
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//
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if (BootMode != BOOT_ON_FLASH_UPDATE && BootMode != BOOT_IN_RECOVERY_MODE) {
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//
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// Galileo Platform UART0 support.
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//
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Type = (EFI_PLATFORM_TYPE)PcdGet16 (PcdPlatformType);
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if (Type == Galileo) {
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//
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// Use MUX to connect out UART0 pins.
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//
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PlatformInitializeUart0MuxGalileo ();
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}
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//
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// GalileoGen2 Platform UART0 support.
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//
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if (Type == GalileoGen2) {
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//
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// Use route out UART0 pins.
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//
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PlatformInitializeUart0MuxGalileoGen2 ();
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}
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}
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}
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EFI_STATUS
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EFIAPI
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CreateConfigEvents (
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VOID
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)
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/*++
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Routine Description:
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Arguments:
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None
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Returns:
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EFI_STATUS
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--*/
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{
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EFI_EVENT EventSmmCfg;
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EFI_EVENT EventSpiReady;
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VOID *RegistrationSmmCfg;
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VOID *RegistrationSpiReady;
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//
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// Schedule callback for when SmmConfigurationProtocol installed.
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//
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EventSmmCfg = EfiCreateProtocolNotifyEvent (
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&gEfiSmmConfigurationProtocolGuid,
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TPL_CALLBACK,
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PlatformConfigOnSmmConfigurationProtocol,
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NULL,
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&RegistrationSmmCfg
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);
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ASSERT (EventSmmCfg != NULL);
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//
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// Schedule callback to setup SPI Flash Policy when SPI interface ready.
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//
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EventSpiReady = EfiCreateProtocolNotifyEvent (
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&gEfiSmmSpiReadyProtocolGuid,
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TPL_CALLBACK,
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PlatformConfigOnSpiReady,
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NULL,
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&RegistrationSpiReady
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);
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ASSERT (EventSpiReady != NULL);
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return EFI_SUCCESS;
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}
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