7ede80607b
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Qian Yi <yi.qian@intel.com> Reviewed-by: Zailing Sun <zailiang.sun@intel.com>
60 lines
1.6 KiB
Plaintext
60 lines
1.6 KiB
Plaintext
/**************************************************************************;
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;* *;
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;* *;
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;* Intel Corporation - ACPI Reference Code for the Baytrail *;
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;* Family of Customer Reference Boards. *;
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;* *;
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;* *;
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;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;
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;
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;* *;
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;* *;
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;**************************************************************************/
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// LPC Bridge - Device 31, Function 0
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// Define the needed LPC registers used by ASL.
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scope(\_SB)
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{
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OperationRegion(ILBR, SystemMemory, \IBAS, 0x8C)
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Field(ILBR, AnyAcc, NoLock, Preserve)
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{
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Offset(0x08), // 0x08
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PARC, 8,
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PBRC, 8,
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PCRC, 8,
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PDRC, 8,
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PERC, 8,
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PFRC, 8,
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PGRC, 8,
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PHRC, 8,
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Offset(0x88), // 0x88
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, 3,
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UI3E, 1,
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UI4E, 1
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}
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Include ("98_LINK.ASL")
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}
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OperationRegion(LPC0, PCI_Config, 0x00, 0xC0)
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Field(LPC0, AnyAcc, NoLock, Preserve)
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{
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Offset(0x08), // 0x08
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SRID, 8, // Revision ID
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Offset(0x080), // 0x80
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C1EN, 1, // COM1 Enable
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, 31
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}
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Include ("LPC_DEV.ASL")
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