7ede80607b
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Qian Yi <yi.qian@intel.com> Reviewed-by: Zailing Sun <zailiang.sun@intel.com>
49 lines
1.7 KiB
C
49 lines
1.7 KiB
C
/**
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Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@file
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PchRegsRcrb.h
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@brief
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Register names for VLV Chipset Configuration Registers
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Conventions:
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- Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values of bits within the registers
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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- In general, PCH registers are denoted by "_PCH_" in register names
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- Registers / bits that are different between PCH generations are denoted by
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"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
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- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
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at the end of the register/bit names
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- Registers / bits of new devices introduced in a PCH generation will be just named
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as "_PCH_" without <generation_name> inserted.
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**/
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#ifndef _PCH_REGS_RCRB_H_
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#define _PCH_REGS_RCRB_H_
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///
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/// Chipset Configuration Registers (Memory space)
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/// RCBA
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///
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#define R_PCH_RCRB_GCS 0x00 // General Control and Status
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#define B_PCH_RCRB_GCS_BBSIZE (BIT30 | BIT29) // Boot Block Size
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#define B_PCH_RCRB_GCS_BBS (BIT11 | BIT10) // Boot BIOS Straps
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#define V_PCH_RCRB_GCS_BBS_SPI (3 << 10) // Boot BIOS strapped to SPI
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#define V_PCH_RCRB_GCS_BBS_LPC (0 << 10) // Boot BIOS strapped to LPC
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#define B_PCH_RCRB_GCS_TS BIT1 // Top Swap
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#define B_PCH_RCRB_GCS_BILD BIT0 // BIOS Interface Lock-Down
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#endif
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