4059386c70
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
148 lines
3.5 KiB
ArmAsm
148 lines
3.5 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# Copyright (c) 2011, ARM. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#------------------------------------------------------------------------------
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.text
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.align 2
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GCC_ASM_EXPORT(__aeabi_uidiv)
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GCC_ASM_EXPORT(__aeabi_uidivmod)
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GCC_ASM_EXPORT(__aeabi_idiv)
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GCC_ASM_EXPORT(__aeabi_idivmod)
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# AREA Math, CODE, READONLY
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#
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#UINT32
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#EFIAPI
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#__aeabi_uidivmode (
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# IN UINT32 Dividen
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# IN UINT32 Divisor
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# );
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#
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ASM_PFX(__aeabi_uidiv):
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ASM_PFX(__aeabi_uidivmod):
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rsbs r12, r1, r0, LSR #4
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mov r2, #0
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bcc ASM_PFX(__arm_div4)
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rsbs r12, r1, r0, LSR #8
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bcc ASM_PFX(__arm_div8)
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mov r3, #0
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b ASM_PFX(__arm_div_large)
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#
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#INT32
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#EFIAPI
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#__aeabi_idivmode (
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# IN INT32 Dividen
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# IN INT32 Divisor
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# );
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#
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ASM_PFX(__aeabi_idiv):
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ASM_PFX(__aeabi_idivmod):
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orrs r12, r0, r1
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bmi ASM_PFX(__arm_div_negative)
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rsbs r12, r1, r0, LSR #1
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mov r2, #0
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bcc ASM_PFX(__arm_div1)
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rsbs r12, r1, r0, LSR #4
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bcc ASM_PFX(__arm_div4)
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rsbs r12, r1, r0, LSR #8
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bcc ASM_PFX(__arm_div8)
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mov r3, #0
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b ASM_PFX(__arm_div_large)
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ASM_PFX(__arm_div8):
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rsbs r12, r1, r0, LSR #7
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subcs r0, r0, r1, LSL #7
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adc r2, r2, r2
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rsbs r12, r1, r0,LSR #6
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subcs r0, r0, r1, LSL #6
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adc r2, r2, r2
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rsbs r12, r1, r0, LSR #5
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subcs r0, r0, r1, LSL #5
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adc r2, r2, r2
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rsbs r12, r1, r0, LSR #4
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subcs r0, r0, r1, LSL #4
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adc r2, r2, r2
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ASM_PFX(__arm_div4):
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rsbs r12, r1, r0, LSR #3
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subcs r0, r0, r1, LSL #3
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adc r2, r2, r2
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rsbs r12, r1, r0, LSR #2
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subcs r0, r0, r1, LSL #2
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adcs r2, r2, r2
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rsbs r12, r1, r0, LSR #1
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subcs r0, r0, r1, LSL #1
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adc r2, r2, r2
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ASM_PFX(__arm_div1):
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subs r1, r0, r1
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movcc r1, r0
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adc r0, r2, r2
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bx r14
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ASM_PFX(__arm_div_negative):
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ands r2, r1, #0x80000000
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rsbmi r1, r1, #0
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eors r3, r2, r0, ASR #32
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rsbcs r0, r0, #0
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rsbs r12, r1, r0, LSR #4
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bcc label1
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rsbs r12, r1, r0, LSR #8
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bcc label2
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ASM_PFX(__arm_div_large):
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lsl r1, r1, #6
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rsbs r12, r1, r0, LSR #8
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orr r2, r2, #0xfc000000
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bcc label2
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lsl r1, r1, #6
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rsbs r12, r1, r0, LSR #8
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orr r2, r2, #0x3f00000
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bcc label2
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lsl r1, r1, #6
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rsbs r12, r1, r0, LSR #8
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orr r2, r2, #0xfc000
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orrcs r2, r2, #0x3f00
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lslcs r1, r1, #6
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rsbs r12, r1, #0
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bcs ASM_PFX(__aeabi_idiv0)
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label3:
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lsrcs r1, r1, #6
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label2:
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rsbs r12, r1, r0, LSR #7
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subcs r0, r0, r1, LSL #7
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adc r2, r2, r2
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rsbs r12, r1, r0, LSR #6
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subcs r0, r0, r1, LSL #6
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adc r2, r2, r2
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rsbs r12, r1, r0, LSR #5
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subcs r0, r0, r1, LSL #5
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adc r2, r2, r2
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rsbs r12, r1, r0, LSR #4
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subcs r0, r0, r1, LSL #4
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adc r2, r2, r2
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label1:
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rsbs r12, r1, r0, LSR #3
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subcs r0, r0, r1, LSL #3
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adc r2, r2, r2
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rsbs r12, r1, r0, LSR #2
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subcs r0, r0, r1, LSL #2
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adcs r2, r2, r2
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bcs label3
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rsbs r12, r1, r0, LSR #1
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subcs r0, r0, r1, LSL #1
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adc r2, r2, r2
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subs r1, r0, r1
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movcc r1, r0
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adc r0, r2, r2
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asrs r3, r3, #31
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rsbmi r0, r0, #0
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rsbcs r1, r1, #0
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bx r14
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@ What to do about division by zero? For now, just return.
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ASM_PFX(__aeabi_idiv0):
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bx r14
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