3402aac7d9
Trailing spaces create issue/warning when generating/applying patches. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
58 lines
2.3 KiB
C
58 lines
2.3 KiB
C
/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef _SP804_TIMER_H__
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#define _SP804_TIMER_H__
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// SP804 Timer constants
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// Note: The SP804 Timer module comprises two timers, Timer_0 and Timer_1
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// These timers are identical and all their registers have an offset of 0x20
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// i.e. SP804_TIMER_0_LOAD_REG = 0x00 and SP804_TIMER_1_LOAD_REG = 0x20
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// Therefore, define all registers only once and adjust the base addresses by 0x20
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#define SP804_TIMER_LOAD_REG 0x00
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#define SP804_TIMER_CURRENT_REG 0x04
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#define SP804_TIMER_CONTROL_REG 0x08
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#define SP804_TIMER_INT_CLR_REG 0x0C
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#define SP804_TIMER_RAW_INT_STS_REG 0x10
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#define SP804_TIMER_MSK_INT_STS_REG 0x14
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#define SP804_TIMER_BG_LOAD_REG 0x18
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// Timer control register bit definitions
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#define SP804_TIMER_CTRL_ONESHOT BIT0
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#define SP804_TIMER_CTRL_32BIT BIT1
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#define SP804_TIMER_CTRL_PRESCALE_MASK (BIT3|BIT2)
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#define SP804_PRESCALE_DIV_1 0
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#define SP804_PRESCALE_DIV_16 BIT2
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#define SP804_PRESCALE_DIV_256 BIT3
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#define SP804_TIMER_CTRL_INT_ENABLE BIT5
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#define SP804_TIMER_CTRL_PERIODIC BIT6
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#define SP804_TIMER_CTRL_ENABLE BIT7
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// Other SP804 Timer definitions
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#define SP804_MAX_TICKS 0xFFFFFFFF
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// SP810 System Controller constants
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#define SP810_SYS_CTRL_REG 0x00
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#define SP810_SYS_CTRL_TIMER0_TIMCLK BIT15 // 0=REFCLK, 1=TIMCLK
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#define SP810_SYS_CTRL_TIMER0_EN BIT16
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#define SP810_SYS_CTRL_TIMER1_TIMCLK BIT17 // 0=REFCLK, 1=TIMCLK
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#define SP810_SYS_CTRL_TIMER1_EN BIT18
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#define SP810_SYS_CTRL_TIMER2_TIMCLK BIT19 // 0=REFCLK, 1=TIMCLK
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#define SP810_SYS_CTRL_TIMER2_EN BIT20
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#define SP810_SYS_CTRL_TIMER3_TIMCLK BIT21 // 0=REFCLK, 1=TIMCLK
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#define SP810_SYS_CTRL_TIMER3_EN BIT22
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#endif
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