8a1f2378d7
According to the ACPI 6.0/6.1 spec, the physical base address of GICC, GICD, GICR and GIC ITS is 64-bit. So change the type of the various GIC base address PCDs to 64-bit, and fix up all users. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Dennis Chen <dennis.chen@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
122 lines
4.3 KiB
C
122 lines
4.3 KiB
C
/** @file
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*
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* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <PiPei.h>
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#include <Library/ArmLib.h>
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#include <Library/ArmGicLib.h>
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#include <Library/ArmPlatformLib.h>
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#include <Library/ArmPlatformSecLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PrintLib.h>
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#include <Library/SerialPortLib.h>
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// When the firmware is built as not Standalone, the secondary cores need to wait the firmware
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// entirely written into DRAM. It is the firmware from DRAM which will wake up the secondary cores.
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VOID
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NonSecureWaitForFirmware (
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VOID
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)
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{
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VOID (*SecondaryStart)(VOID);
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UINTN AcknowledgeInterrupt;
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UINTN InterruptId;
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// The secondary cores will execute the firmware once wake from WFI.
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SecondaryStart = (VOID (*)())(UINTN)PcdGet64 (PcdFvBaseAddress);
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ArmCallWFI ();
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// Acknowledge the interrupt and send End of Interrupt signal.
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AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), &InterruptId);
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// Check if it is a valid interrupt ID
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if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet64 (PcdGicDistributorBase))) {
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// Got a valid SGI number hence signal End of Interrupt
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ArmGicEndOfInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);
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}
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// Jump to secondary core entry point.
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SecondaryStart ();
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// PEI Core should always load and never return
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ASSERT (FALSE);
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}
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/**
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Call before jumping to Normal World
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This function allows the firmware platform to do extra actions before
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jumping to the Normal World
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**/
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VOID
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ArmPlatformSecExtraAction (
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IN UINTN MpId,
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OUT UINTN* JumpAddress
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)
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{
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CHAR8 Buffer[100];
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UINTN CharCount;
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UINTN* StartAddress;
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if (FeaturePcdGet (PcdStandalone) == FALSE) {
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//
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// Warning: This code assumes the DRAM has already been initialized by ArmPlatformSecLib
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//
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if (ArmPlatformIsPrimaryCore (MpId)) {
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StartAddress = (UINTN*)(UINTN)PcdGet64 (PcdFvBaseAddress);
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// Patch the DRAM to make an infinite loop at the start address
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*StartAddress = 0xEAFFFFFE; // opcode for while(1)
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Waiting for firmware at 0x%08X ...\n\r",StartAddress);
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SerialPortWrite ((UINT8 *) Buffer, CharCount);
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*JumpAddress = PcdGet64 (PcdFvBaseAddress);
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} else {
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// When the primary core is stopped by the hardware debugger to copy the firmware
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// into DRAM. The secondary cores are still running. As soon as the first bytes of
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// the firmware are written into DRAM, the secondary cores will start to execute the
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// code even if the firmware is not entirely written into the memory.
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// That's why the secondary cores need to be parked in WFI and wake up once the
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// firmware is ready.
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*JumpAddress = (UINTN)NonSecureWaitForFirmware;
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}
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} else if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {
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//
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// Warning: This code assumes the DRAM has already been initialized by ArmPlatformSecLib
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//
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if (ArmPlatformIsPrimaryCore (MpId)) {
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// Signal the secondary cores they can jump to PEI phase
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ArmGicSendSgiTo (PcdGet64 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
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// To enter into Non Secure state, we need to make a return from exception
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*JumpAddress = PcdGet64 (PcdFvBaseAddress);
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} else {
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// We wait for the primary core to finish to initialize the System Memory. Otherwise the secondary
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// cores would make crash the system by setting their stacks in DRAM before the primary core has not
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// finished to initialize the system memory.
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*JumpAddress = (UINTN)NonSecureWaitForFirmware;
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}
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} else {
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*JumpAddress = PcdGet64 (PcdFvBaseAddress);
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}
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}
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