8a08dc5486
The ACPI 6.3 specification introduces a 'SPE overflow Interrupt' field as part of the GICC structure. Update the MADT parser to decode this field and validate the interrupt ID used. References: - ACPI 6.3 Specification - January 2019 - Arm Generic Interrupt Controller Architecture Specification, GIC architecture version 3 and version 4, issue E - Arm Server Base System Architecture 5.0 Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com> Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
41 lines
1.4 KiB
C
41 lines
1.4 KiB
C
/** @file
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Header file for MADT table parser
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Copyright (c) 2019, ARM Limited. All rights reserved.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Reference(s):
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- Arm Generic Interrupt Controller Architecture Specification,
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GIC architecture version 3 and version 4, issue E
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- Arm Server Base System Architecture 5.0
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**/
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#ifndef MADT_PARSER_H_
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#define MADT_PARSER_H_
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///
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/// Level 3 base server system Private Peripheral Inerrupt (PPI) ID assignments
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///
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#define ARM_PPI_ID_OVERFLOW_INTERRUPT_FROM_CNTP 30
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#define ARM_PPI_ID_OVERFLOW_INTERRUPT_FROM_CNTPS 29
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#define ARM_PPI_ID_OVERFLOW_INTERRUPT_FROM_CNTHV 28
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#define ARM_PPI_ID_OVERFLOW_INTERRUPT_FROM_CNTV 27
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#define ARM_PPI_ID_OVERFLOW_INTERRUPT_FROM_CNTHP 26
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#define ARM_PPI_ID_GIC_MAINTENANCE_INTERRUPT 25
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#define ARM_PPI_ID_CTIIRQ 24
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#define ARM_PPI_ID_PERFORMANCE_MONITORS_INTERRUPT 23
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#define ARM_PPI_ID_COMMIRQ 22
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#define ARM_PPI_ID_PMBIRQ 21
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#define ARM_PPI_ID_CNTHPS 20
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#define ARM_PPI_ID_CNTHVS 19
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///
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/// PPI ID allowed ranges
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///
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#define ARM_PPI_ID_MAX 31
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#define ARM_PPI_ID_MIN 16
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#define ARM_PPI_ID_EXTENDED_MAX 1119
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#define ARM_PPI_ID_EXTENDED_MIN 1056
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#endif // MADT_PARSER_H_
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