6995a1b79b
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 A GHCB page is needed during the Sec phase, so this new page must be created. Since the #VC exception handler routines assume that a per-CPU variable area is immediately after the GHCB, this per-CPU variable area must also be created. Since the GHCB must be marked as an un-encrypted, or shared, page, an additional pagetable page is required to break down the 2MB region where the GHCB page lives into 4K pagetable entries. Create a new entry in the OVMF memory layout for the new page table page and for the SEC GHCB and per-CPU variable pages. After breaking down the 2MB page, update the GHCB page table entry to remove the encryption mask. The GHCB page will be used by the SEC #VC exception handler. The #VC exception handler will fill in the necessary fields of the GHCB and exit to the hypervisor using the VMGEXIT instruction. The hypervisor then accesses the GHCB in order to perform the requested function. Four new fixed PCDs are needed to support the SEC GHCB page: - PcdOvmfSecGhcbBase UINT32 value that is the base address of the GHCB used during the SEC phase. - PcdOvmfSecGhcbSize UINT32 value that is the size, in bytes, of the GHCB area used during the SEC phase. - PcdOvmfSecGhcbPageTableBase UINT32 value that is address of a page table page used to break down the 2MB page into 512 4K pages. - PcdOvmfSecGhcbPageTableSize UINT32 value that is the size, in bytes, of the page table page. Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
225 lines
6.3 KiB
NASM
225 lines
6.3 KiB
NASM
;------------------------------------------------------------------------------
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; @file
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; Sets the CR3 register for 64-bit paging
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;
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; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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BITS 32
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%define PAGE_PRESENT 0x01
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%define PAGE_READ_WRITE 0x02
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%define PAGE_USER_SUPERVISOR 0x04
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%define PAGE_WRITE_THROUGH 0x08
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%define PAGE_CACHE_DISABLE 0x010
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%define PAGE_ACCESSED 0x020
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%define PAGE_DIRTY 0x040
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%define PAGE_PAT 0x080
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%define PAGE_GLOBAL 0x0100
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%define PAGE_2M_MBO 0x080
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%define PAGE_2M_PAT 0x01000
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%define PAGE_4K_PDE_ATTR (PAGE_ACCESSED + \
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PAGE_DIRTY + \
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PAGE_READ_WRITE + \
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PAGE_PRESENT)
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%define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \
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PAGE_ACCESSED + \
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PAGE_DIRTY + \
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PAGE_READ_WRITE + \
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PAGE_PRESENT)
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%define PAGE_PDP_ATTR (PAGE_ACCESSED + \
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PAGE_READ_WRITE + \
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PAGE_PRESENT)
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; Check if Secure Encrypted Virtualization (SEV) feature is enabled
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;
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; If SEV is enabled then EAX will be at least 32
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; If SEV is disabled then EAX will be zero.
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;
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CheckSevFeature:
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; Check if we have a valid (0x8000_001F) CPUID leaf
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mov eax, 0x80000000
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cpuid
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; This check should fail on Intel or Non SEV AMD CPUs. In future if
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; Intel CPUs supports this CPUID leaf then we are guranteed to have exact
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; same bit definition.
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cmp eax, 0x8000001f
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jl NoSev
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; Check for memory encryption feature:
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; CPUID Fn8000_001F[EAX] - Bit 1
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;
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mov eax, 0x8000001f
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cpuid
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bt eax, 1
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jnc NoSev
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; Check if memory encryption is enabled
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; MSR_0xC0010131 - Bit 0 (SEV enabled)
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mov ecx, 0xc0010131
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rdmsr
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bt eax, 0
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jnc NoSev
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; Get pte bit position to enable memory encryption
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; CPUID Fn8000_001F[EBX] - Bits 5:0
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;
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mov eax, ebx
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and eax, 0x3f
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jmp SevExit
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NoSev:
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xor eax, eax
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SevExit:
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OneTimeCallRet CheckSevFeature
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; Check if Secure Encrypted Virtualization - Encrypted State (SEV-ES) feature
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; is enabled.
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;
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; Modified: EAX, EBX, ECX
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;
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; If SEV-ES is enabled then EAX will be non-zero.
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; If SEV-ES is disabled then EAX will be zero.
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;
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CheckSevEsFeature:
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xor eax, eax
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; SEV-ES can't be enabled if SEV isn't, so first check the encryption
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; mask.
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test edx, edx
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jz NoSevEs
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; Save current value of encryption mask
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mov ebx, edx
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; Check if SEV-ES is enabled
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; MSR_0xC0010131 - Bit 1 (SEV-ES enabled)
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mov ecx, 0xc0010131
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rdmsr
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and eax, 2
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; Restore encryption mask
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mov edx, ebx
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NoSevEs:
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OneTimeCallRet CheckSevEsFeature
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;
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; Modified: EAX, EBX, ECX, EDX
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;
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SetCr3ForPageTables64:
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OneTimeCall CheckSevFeature
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xor edx, edx
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test eax, eax
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jz SevNotActive
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; If SEV is enabled, C-bit is always above 31
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sub eax, 32
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bts edx, eax
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SevNotActive:
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;
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; For OVMF, build some initial page tables at
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; PcdOvmfSecPageTablesBase - (PcdOvmfSecPageTablesBase + 0x6000).
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;
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; This range should match with PcdOvmfSecPageTablesSize which is
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; declared in the FDF files.
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;
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; At the end of PEI, the pages tables will be rebuilt into a
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; more permanent location by DxeIpl.
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;
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mov ecx, 6 * 0x1000 / 4
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xor eax, eax
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clearPageTablesMemoryLoop:
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mov dword[ecx * 4 + PT_ADDR (0) - 4], eax
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loop clearPageTablesMemoryLoop
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;
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; Top level Page Directory Pointers (1 * 512GB entry)
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;
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mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDP_ATTR
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mov dword[PT_ADDR (4)], edx
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;
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; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
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;
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mov dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDP_ATTR
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mov dword[PT_ADDR (0x1004)], edx
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mov dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDP_ATTR
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mov dword[PT_ADDR (0x100C)], edx
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mov dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDP_ATTR
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mov dword[PT_ADDR (0x1014)], edx
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mov dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDP_ATTR
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mov dword[PT_ADDR (0x101C)], edx
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;
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; Page Table Entries (2048 * 2MB entries => 4GB)
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;
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mov ecx, 0x800
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pageTableEntriesLoop:
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mov eax, ecx
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dec eax
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shl eax, 21
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add eax, PAGE_2M_PDE_ATTR
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mov [ecx * 8 + PT_ADDR (0x2000 - 8)], eax
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mov [(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], edx
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loop pageTableEntriesLoop
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OneTimeCall CheckSevEsFeature
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test eax, eax
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jz SetCr3
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;
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; The initial GHCB will live at GHCB_BASE and needs to be un-encrypted.
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; This requires the 2MB page for this range be broken down into 512 4KB
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; pages. All will be marked encrypted, except for the GHCB.
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;
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mov ecx, (GHCB_BASE >> 21)
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mov eax, GHCB_PT_ADDR + PAGE_PDP_ATTR
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mov [ecx * 8 + PT_ADDR (0x2000)], eax
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;
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; Page Table Entries (512 * 4KB entries => 2MB)
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;
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mov ecx, 512
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pageTableEntries4kLoop:
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mov eax, ecx
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dec eax
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shl eax, 12
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add eax, GHCB_BASE & 0xFFE0_0000
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add eax, PAGE_4K_PDE_ATTR
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mov [ecx * 8 + GHCB_PT_ADDR - 8], eax
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mov [(ecx * 8 + GHCB_PT_ADDR - 8) + 4], edx
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loop pageTableEntries4kLoop
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;
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; Clear the encryption bit from the GHCB entry
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;
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mov ecx, (GHCB_BASE & 0x1F_FFFF) >> 12
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mov [ecx * 8 + GHCB_PT_ADDR + 4], strict dword 0
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mov ecx, GHCB_SIZE / 4
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xor eax, eax
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clearGhcbMemoryLoop:
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mov dword[ecx * 4 + GHCB_BASE - 4], eax
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loop clearGhcbMemoryLoop
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SetCr3:
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;
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; Set CR3 now that the paging structures are available
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;
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mov eax, PT_ADDR (0)
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mov cr3, eax
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OneTimeCallRet SetCr3ForPageTables64
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