903e31242d
Annotate functions with ASM_FUNC() so that they are emitted into separate sections. Note that in some cases, various entry points refer to different parts of the same routine, so in those cases, the files have been left untouched. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
243 lines
4.6 KiB
ArmAsm
243 lines
4.6 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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#include <AsmMacroIoLib.h>
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.syntax unified
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ASM_FUNC(__udivmoddi4)
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stmfd sp!, {r4, r5, r6, r7, lr}
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add r7, sp, #12
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stmfd sp!, {r10, r11}
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sub sp, sp, #20
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stmia sp, {r2-r3}
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ldr r6, [sp, #48]
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orrs r2, r2, r3
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mov r10, r0
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mov r11, r1
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beq L2
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subs ip, r1, #0
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bne L4
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cmp r3, #0
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bne L6
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cmp r6, #0
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beq L8
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mov r1, r2
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bl ASM_PFX(__umodsi3)
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mov r1, #0
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stmia r6, {r0-r1}
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L8:
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ldr r1, [sp, #0]
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mov r0, r10
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b L45
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L6:
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cmp r6, #0
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movne r1, #0
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stmiane r6, {r0-r1}
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b L2
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L4:
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ldr r1, [sp, #0]
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cmp r1, #0
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bne L12
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ldr r2, [sp, #4]
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cmp r2, #0
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bne L14
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cmp r6, #0
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beq L16
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mov r1, r2
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mov r0, r11
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bl ASM_PFX(__umodsi3)
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mov r1, #0
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stmia r6, {r0-r1}
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L16:
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ldr r1, [sp, #4]
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mov r0, r11
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L45:
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bl ASM_PFX(__udivsi3)
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L46:
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mov r10, r0
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mov r11, #0
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b L10
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L14:
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subs r1, r0, #0
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bne L18
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cmp r6, #0
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beq L16
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ldr r1, [sp, #4]
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mov r0, r11
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bl ASM_PFX(__umodsi3)
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mov r4, r10
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mov r5, r0
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stmia r6, {r4-r5}
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b L16
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L18:
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sub r3, r2, #1
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tst r2, r3
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bne L22
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cmp r6, #0
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movne r4, r0
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andne r5, ip, r3
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stmiane r6, {r4-r5}
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L24:
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rsb r3, r2, #0
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and r3, r2, r3
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clz r3, r3
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rsb r3, r3, #31
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mov r0, ip, lsr r3
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b L46
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L22:
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clz r2, r2
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clz r3, ip
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rsb r3, r3, r2
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cmp r3, #30
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bhi L48
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rsb r2, r3, #31
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add lr, r3, #1
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mov r3, r1, asl r2
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str r3, [sp, #12]
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mov r3, r1, lsr lr
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ldr r0, [sp, #0]
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mov r5, ip, lsr lr
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orr r4, r3, ip, asl r2
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str r0, [sp, #8]
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b L29
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L12:
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ldr r3, [sp, #4]
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cmp r3, #0
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bne L30
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sub r3, r1, #1
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tst r1, r3
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bne L32
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cmp r6, #0
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andne r3, r3, r0
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movne r2, r3
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movne r3, #0
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stmiane r6, {r2-r3}
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L34:
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cmp r1, #1
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beq L10
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rsb r3, r1, #0
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and r3, r1, r3
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clz r3, r3
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rsb r0, r3, #31
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mov r1, ip, lsr r0
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rsb r3, r0, #32
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mov r0, r10, lsr r0
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orr ip, r0, ip, asl r3
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str r1, [sp, #12]
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str ip, [sp, #8]
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ldrd r10, [sp, #8]
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b L10
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L32:
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clz r2, r1
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clz r3, ip
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rsb r3, r3, r2
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rsb r4, r3, #31
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mov r2, r0, asl r4
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mvn r1, r3
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and r2, r2, r1, asr #31
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add lr, r3, #33
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str r2, [sp, #8]
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add r2, r3, #1
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mov r3, r3, asr #31
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and r0, r3, r0, asl r1
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mov r3, r10, lsr r2
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orr r3, r3, ip, asl r4
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and r3, r3, r1, asr #31
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orr r0, r0, r3
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mov r3, ip, lsr lr
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str r0, [sp, #12]
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mov r0, r10, lsr lr
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and r5, r3, r2, asr #31
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rsb r3, lr, #31
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mov r3, r3, asr #31
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orr r0, r0, ip, asl r1
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and r3, r3, ip, lsr r2
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and r0, r0, r2, asr #31
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orr r4, r3, r0
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b L29
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L30:
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clz r2, r3
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clz r3, ip
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rsb r3, r3, r2
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cmp r3, #31
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bls L37
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L48:
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cmp r6, #0
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stmiane r6, {r10-r11}
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b L2
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L37:
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rsb r1, r3, #31
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mov r0, r0, asl r1
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add lr, r3, #1
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mov r2, #0
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str r0, [sp, #12]
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mov r0, r10, lsr lr
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str r2, [sp, #8]
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sub r2, r3, #31
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and r0, r0, r2, asr #31
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mov r3, ip, lsr lr
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orr r4, r0, ip, asl r1
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and r5, r3, r2, asr #31
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L29:
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mov ip, #0
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mov r10, ip
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b L40
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L41:
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ldr r1, [sp, #12]
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ldr r2, [sp, #8]
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mov r3, r4, lsr #31
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orr r5, r3, r5, asl #1
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mov r3, r1, lsr #31
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orr r4, r3, r4, asl #1
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mov r3, r2, lsr #31
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orr r0, r3, r1, asl #1
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orr r1, ip, r2, asl #1
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ldmia sp, {r2-r3}
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str r0, [sp, #12]
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subs r2, r2, r4
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sbc r3, r3, r5
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str r1, [sp, #8]
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subs r0, r2, #1
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sbc r1, r3, #0
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mov r2, r1, asr #31
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ldmia sp, {r0-r1}
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mov r3, r2
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and ip, r2, #1
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and r3, r3, r1
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and r2, r2, r0
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subs r4, r4, r2
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sbc r5, r5, r3
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add r10, r10, #1
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L40:
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cmp r10, lr
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bne L41
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ldrd r0, [sp, #8]
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adds r0, r0, r0
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adc r1, r1, r1
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cmp r6, #0
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orr r10, r0, ip
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mov r11, r1
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stmiane r6, {r4-r5}
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b L10
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L2:
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mov r10, #0
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mov r11, #0
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L10:
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mov r0, r10
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mov r1, r11
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sub sp, r7, #20
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ldmfd sp!, {r10, r11}
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ldmfd sp!, {r4, r5, r6, r7, pc}
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