On ARM systems, mapping normal memory as device memory may have unintended side effects, given that unaligned accesses or loads and stores with special semantics (e.g., load/store exclusive) may fault or may not work as expected. Similarly, DC ZVA instructions are only supported on normal memory, not device memory. So remove the EFI_MEMORY_UC attribute that we set by default on system RAM. If any region requires this attribute, it is up to the driver to set this attribute, and to ensure that no offending operations are performed on it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
174 lines
7.4 KiB
C
174 lines
7.4 KiB
C
/** @file
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*
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* Copyright (c) 2013-2015, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Library/ArmPlatformLib.h>
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <Library/PcdLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <ArmPlatform.h>
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// The total number of descriptors, including the final "end-of-table" descriptor.
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#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 16
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// DDR attributes
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#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
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#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
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/**
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Return the Virtual Memory Map of your platform
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This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
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@param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
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Virtual Memory mapping. This array must be ended by a zero-filled
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entry
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**/
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VOID
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ArmPlatformGetVirtualMemoryMap (
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IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
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)
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{
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ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
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UINTN Index = 0;
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ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
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EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
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ASSERT (VirtualMemoryMap != NULL);
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//
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// Declared the additional 6GB of memory
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//
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ResourceAttributes =
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_TESTED;
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BuildResourceDescriptorHob (
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EFI_RESOURCE_SYSTEM_MEMORY,
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ResourceAttributes,
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ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE,
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ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ);
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VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
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if (VirtualMemoryTable == NULL) {
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return;
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}
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if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
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CacheAttributes = DDR_ATTRIBUTES_CACHED;
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} else {
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CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
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}
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// SMB CS0 - NOR0 Flash
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VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;
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VirtualMemoryTable[Index].Length = SIZE_256KB * 255;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// Environment Variables region
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);
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VirtualMemoryTable[Index].Length = SIZE_64KB * 4;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// SMB CS2 & CS3 - Off-chip (motherboard) peripherals
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_SMB_PERIPH_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// Juno OnChip non-secure ROM
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VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_NON_SECURE_ROM_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_NON_SECURE_ROM_BASE;
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VirtualMemoryTable[Index].Length = ARM_JUNO_NON_SECURE_ROM_SZ;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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// Juno OnChip peripherals
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VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_PERIPHERALS_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_PERIPHERALS_BASE;
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VirtualMemoryTable[Index].Length = ARM_JUNO_PERIPHERALS_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// Juno OnChip non-secure SRAM
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VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_NON_SECURE_SRAM_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_NON_SECURE_SRAM_BASE;
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VirtualMemoryTable[Index].Length = ARM_JUNO_NON_SECURE_SRAM_SZ;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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// PCI Root Complex
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VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPcieControlBaseAddress);
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VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPcieControlBaseAddress);
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VirtualMemoryTable[Index].Length = SIZE_128KB;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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//
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// PCI Configuration Space
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//
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VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciConfigurationSpaceBaseAddress);
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VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciConfigurationSpaceBaseAddress);
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VirtualMemoryTable[Index].Length = PcdGet64 (PcdPciConfigurationSpaceSize);
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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//
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// PCI Memory Space
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//
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VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdPciMmio32Base);
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VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdPciMmio32Base);
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VirtualMemoryTable[Index].Length = PcdGet32 (PcdPciMmio32Size);
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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//
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// 64-bit PCI Memory Space
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//
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VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciMmio64Base);
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VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciMmio64Base);
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VirtualMemoryTable[Index].Length = PcdGet64 (PcdPciMmio64Size);
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// Juno SOC peripherals
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VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_SOC_PERIPHERALS_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_SOC_PERIPHERALS_BASE;
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VirtualMemoryTable[Index].Length = ARM_JUNO_SOC_PERIPHERALS_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// DDR - 2GB
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VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
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VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);
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VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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// DDR - 6GB
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VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE;
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VirtualMemoryTable[Index].Length = ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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// End of Table
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VirtualMemoryTable[++Index].PhysicalBase = 0;
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VirtualMemoryTable[Index].VirtualBase = 0;
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VirtualMemoryTable[Index].Length = 0;
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VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
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ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
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*VirtualMemoryMap = VirtualMemoryTable;
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}
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