4e48c72c4c
Introduce macros to detect the underlying platform and access its ACPI power management registers, based on querying the host bridge device ID. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gabriel Somlo <somlo@cmu.edu> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16372 6f19259b-4bc3-4df7-8a09-765794883524
50 lines
1.5 KiB
C
50 lines
1.5 KiB
C
/** @file
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OVMF Platform definitions
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Copyright (c) 2014, Gabriel L. Somlo <somlo@cmu.edu>
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This program and the accompanying materials are licensed and made
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available under the terms and conditions of the BSD License which
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accompanies this distribution. The full text of the license may
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be found at http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __OVMF_PLATFORMS_H__
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#define __OVMF_PLATFORMS_H__
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#include <Library/PciLib.h>
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#include <IndustryStandard/Pci22.h>
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//
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// Host Bridge Device ID (DID) values for PIIX4 and Q35/MCH
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//
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#define INTEL_82441_DEVICE_ID 0x1237 // PIIX4
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#define INTEL_Q35_MCH_DEVICE_ID 0x29C0 // Q35
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//
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// OVMF Host Bridge DID Address
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//
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#define OVMF_HOSTBRIDGE_DID \
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PCI_LIB_ADDRESS (0, 0, 0, PCI_DEVICE_ID_OFFSET)
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//
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// Power Management Device and Function numbers for PIIX4 and Q35/MCH
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//
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#define OVMF_PM_DEVICE_PIIX4 0x01
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#define OVMF_PM_FUNC_PIIX4 0x03
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#define OVMF_PM_DEVICE_Q35 0x1f
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#define OVMF_PM_FUNC_Q35 0x00
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//
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// Power Management Register access for PIIX4 and Q35/MCH
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//
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#define POWER_MGMT_REGISTER_PIIX4(Offset) \
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PCI_LIB_ADDRESS (0, OVMF_PM_DEVICE_PIIX4, OVMF_PM_FUNC_PIIX4, (Offset))
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#define POWER_MGMT_REGISTER_Q35(Offset) \
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PCI_LIB_ADDRESS (0, OVMF_PM_DEVICE_Q35, OVMF_PM_FUNC_Q35, (Offset))
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#endif
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