70119d2741
No platforms use the ARMv6 (ARM11) support code anymore. In fact, the only reference to it in ArmPkg.dsc was commented out by Andrew in SVN r11298 (2011-02-03) so it may well be broken. So remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18237 6f19259b-4bc3-4df7-8a09-765794883524
191 lines
4.9 KiB
ArmAsm
191 lines
4.9 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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#include <AsmMacroIoLib.h>
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.text
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.align 2
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GCC_ASM_EXPORT(ArmReadMidr)
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GCC_ASM_EXPORT(ArmCacheInfo)
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GCC_ASM_EXPORT(ArmGetInterruptState)
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GCC_ASM_EXPORT(ArmGetFiqState)
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GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
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GCC_ASM_EXPORT(ArmSetTTBR0)
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GCC_ASM_EXPORT(ArmSetDomainAccessControl)
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GCC_ASM_EXPORT(CPSRMaskInsert)
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GCC_ASM_EXPORT(CPSRRead)
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GCC_ASM_EXPORT(ArmReadCpacr)
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GCC_ASM_EXPORT(ArmWriteCpacr)
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GCC_ASM_EXPORT(ArmWriteAuxCr)
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GCC_ASM_EXPORT(ArmReadAuxCr)
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GCC_ASM_EXPORT(ArmInvalidateTlb)
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GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
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GCC_ASM_EXPORT(ArmReadScr)
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GCC_ASM_EXPORT(ArmWriteScr)
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GCC_ASM_EXPORT(ArmReadMVBar)
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GCC_ASM_EXPORT(ArmWriteMVBar)
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GCC_ASM_EXPORT(ArmReadHVBar)
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GCC_ASM_EXPORT(ArmWriteHVBar)
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GCC_ASM_EXPORT(ArmCallWFE)
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GCC_ASM_EXPORT(ArmCallSEV)
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GCC_ASM_EXPORT(ArmReadSctlr)
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GCC_ASM_EXPORT(ArmReadCpuActlr)
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GCC_ASM_EXPORT(ArmWriteCpuActlr)
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#------------------------------------------------------------------------------
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ASM_PFX(ArmReadMidr):
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mrc p15,0,R0,c0,c0,0
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bx LR
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ASM_PFX(ArmCacheInfo):
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mrc p15,0,R0,c0,c0,1
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bx LR
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ASM_PFX(ArmGetInterruptState):
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mrs R0,CPSR
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tst R0,#0x80 @Check if IRQ is enabled.
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moveq R0,#1
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movne R0,#0
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bx LR
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ASM_PFX(ArmGetFiqState):
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mrs R0,CPSR
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tst R0,#0x40 @Check if FIQ is enabled.
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moveq R0,#1
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movne R0,#0
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bx LR
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ASM_PFX(ArmSetDomainAccessControl):
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mcr p15,0,r0,c3,c0,0
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bx lr
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ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
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stmfd sp!, {r4-r12, lr} @ save all the banked registers
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mov r3, sp @ copy the stack pointer into a non-banked register
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mrs r2, cpsr @ read the cpsr
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bic r2, r2, r0 @ clear mask in the cpsr
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and r1, r1, r0 @ clear bits outside the mask in the input
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orr r2, r2, r1 @ set field
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msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
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isb
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mov sp, r3 @ restore stack pointer
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ldmfd sp!, {r4-r12, lr} @ restore registers
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bx lr @ return (hopefully thumb-safe!)
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ASM_PFX(CPSRRead):
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mrs r0, cpsr
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bx lr
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ASM_PFX(ArmReadCpacr):
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mrc p15, 0, r0, c1, c0, 2
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bx lr
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ASM_PFX(ArmWriteCpacr):
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mcr p15, 0, r0, c1, c0, 2
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isb
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bx lr
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ASM_PFX(ArmWriteAuxCr):
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mcr p15, 0, r0, c1, c0, 1
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bx lr
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ASM_PFX(ArmReadAuxCr):
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mrc p15, 0, r0, c1, c0, 1
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bx lr
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ASM_PFX(ArmSetTTBR0):
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mcr p15,0,r0,c2,c0,0
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isb
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bx lr
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ASM_PFX(ArmGetTTBR0BaseAddress):
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mrc p15,0,r0,c2,c0,0
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LoadConstantToReg(0xFFFFC000, r1)
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and r0, r0, r1
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isb
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bx lr
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//
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//VOID
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//ArmUpdateTranslationTableEntry (
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// IN VOID *TranslationTableEntry // R0
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// IN VOID *MVA // R1
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// );
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ASM_PFX(ArmUpdateTranslationTableEntry):
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mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA
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dsb
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mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA
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mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
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dsb
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isb
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bx lr
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ASM_PFX(ArmInvalidateTlb):
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mov r0,#0
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mcr p15,0,r0,c8,c7,0
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mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
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dsb
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isb
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bx lr
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ASM_PFX(ArmReadScr):
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mrc p15, 0, r0, c1, c1, 0
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bx lr
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ASM_PFX(ArmWriteScr):
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mcr p15, 0, r0, c1, c1, 0
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bx lr
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ASM_PFX(ArmReadHVBar):
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mrc p15, 4, r0, c12, c0, 0
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bx lr
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ASM_PFX(ArmWriteHVBar):
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mcr p15, 4, r0, c12, c0, 0
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bx lr
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ASM_PFX(ArmReadMVBar):
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mrc p15, 0, r0, c12, c0, 1
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bx lr
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ASM_PFX(ArmWriteMVBar):
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mcr p15, 0, r0, c12, c0, 1
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bx lr
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ASM_PFX(ArmCallWFE):
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wfe
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bx lr
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ASM_PFX(ArmCallSEV):
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sev
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bx lr
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ASM_PFX(ArmReadSctlr):
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mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
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bx lr
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ASM_PFX(ArmReadCpuActlr):
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mrc p15, 0, r0, c1, c0, 1
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bx lr
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ASM_PFX(ArmWriteCpuActlr):
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mcr p15, 0, r0, c1, c0, 1
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dsb
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isb
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bx lr
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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