73974f809c
Introduce the Q35SmramAtDefaultSmbaseInitialization() function for detecting the "SMRAM at default SMBASE" feature. For now, the function is only a skeleton, so that we can gradually build upon the result while the result is hard-coded as FALSE. The actual detection will occur in a later patch. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1512 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Message-Id: <20200129214412.2361-6-lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
132 lines
1.9 KiB
C
132 lines
1.9 KiB
C
/** @file
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Platform PEI module include file.
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Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PLATFORM_PEI_H_INCLUDED_
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#define _PLATFORM_PEI_H_INCLUDED_
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#include <IndustryStandard/E820.h>
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VOID
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AddIoMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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);
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VOID
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AddIoMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit
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);
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VOID
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AddMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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);
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VOID
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AddMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit
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);
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VOID
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AddReservedMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize,
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BOOLEAN Cacheable
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);
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VOID
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AddressWidthInitialization (
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VOID
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);
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VOID
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Q35TsegMbytesInitialization (
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VOID
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);
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VOID
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Q35SmramAtDefaultSmbaseInitialization (
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VOID
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);
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EFI_STATUS
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PublishPeiMemory (
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VOID
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);
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UINT32
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GetSystemMemorySizeBelow4gb (
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VOID
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);
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VOID
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QemuUc32BaseInitialization (
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VOID
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);
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VOID
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InitializeRamRegions (
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VOID
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);
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EFI_STATUS
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PeiFvInitialization (
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VOID
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);
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VOID
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InstallFeatureControlCallback (
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VOID
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);
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VOID
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InstallClearCacheCallback (
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VOID
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);
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EFI_STATUS
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InitializeXen (
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VOID
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);
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BOOLEAN
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XenDetect (
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VOID
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);
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VOID
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AmdSevInitialize (
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VOID
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);
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extern BOOLEAN mXen;
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VOID
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XenPublishRamRegions (
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VOID
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);
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extern EFI_BOOT_MODE mBootMode;
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extern BOOLEAN mS3Supported;
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extern UINT8 mPhysMemAddressWidth;
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extern UINT32 mMaxCpuCount;
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extern UINT16 mHostBridgeDevId;
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extern BOOLEAN mQ35SmramAtDefaultSmbase;
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extern UINT32 mQemuUc32Base;
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#endif // _PLATFORM_PEI_H_INCLUDED_
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