7601b251fd
Add RISC-V RV64 BaseLib functions. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
26 lines
432 B
C
26 lines
432 B
C
/** @file
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CPU enable interrupt function for RISC-V
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Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "BaseLibInternals.h"
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extern VOID RiscVEnableSupervisorModeInterrupt (VOID);
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/**
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Enables CPU interrupts.
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**/
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VOID
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EFIAPI
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EnableInterrupts (
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VOID
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)
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{
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RiscVEnableSupervisorModeInterrupt ();
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}
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