e35a746cf5
This generator allows to generate a SSDT table describing a Pci express Bus. It uses the following CmObj: - EArmObjCmRef - EArmObjPciConfigSpaceInfo - EArmObjPciAddressMapInfo - EArmObjPciInterruptMapInfo REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3682 To: Sami Mujawar <sami.mujawar@arm.com> To: Alexei Fedorov <Alexei.Fedorov@arm.com> Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
139 lines
4.3 KiB
C
139 lines
4.3 KiB
C
/** @file
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SSDT Pcie Table Generator.
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Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Reference(s):
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- PCI Firmware Specification - Revision 3.0
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- ACPI 6.4 specification:
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- s6.2.13 "_PRT (PCI Routing Table)"
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- s6.1.1 "_ADR (Address)"
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- linux kernel code
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- Arm Base Boot Requirements v1.0
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**/
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#ifndef SSDT_PCIE_GENERATOR_H_
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#define SSDT_PCIE_GENERATOR_H_
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/** Pci address attributes.
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This can also be denoted as space code, address space or ss.
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*/
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#define PCI_SS_CONFIG 0
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#define PCI_SS_IO 1
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#define PCI_SS_M32 2
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#define PCI_SS_M64 3
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/** Maximum Pci root complexes supported by this generator.
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Note: This is not a hard limitation and can be extended if needed.
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Corresponding changes would be needed to support the Name and
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UID fields describing the Pci root complexes.
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*/
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#define MAX_PCI_ROOT_COMPLEXES_SUPPORTED 16
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/** Maximum number of Pci legacy interrupts.
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Currently 4 for INTA-INTB-INTC-INTD.
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*/
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#define MAX_PCI_LEGACY_INTERRUPT 4
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// _SB scope of the AML namespace.
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#define SB_SCOPE "\\_SB_"
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/** C array containing the compiled AML template.
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This symbol is defined in the auto generated C file
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containing the AML bytecode array.
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*/
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extern CHAR8 ssdtpcieosctemplate_aml_code[];
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#pragma pack(1)
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/** Structure used to map integer to an index.
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*/
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typedef struct MappingTable {
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/// Mapping table.
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/// Contains the Index <-> integer mapping
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UINT32 *Table;
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/// Last used index of the Table.
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/// Bound by MaxIndex.
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UINT32 LastIndex;
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/// Number of entries in the Table.
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UINT32 MaxIndex;
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} MAPPING_TABLE;
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/** A structure holding the Pcie generator and additional private data.
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*/
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typedef struct AcpiPcieGenerator {
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/// ACPI Table generator header
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ACPI_TABLE_GENERATOR Header;
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// Private fields are defined from here.
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/** A structure used to handle the Address and Interrupt Map referencing.
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A CM_ARM_PCI_CONFIG_SPACE_INFO structure references two CM_ARM_OBJ_REF:
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- one for the address mapping, referencing
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CM_ARM_PCI_ADDRESS_MAP_INFO structures.
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- one for the interrupt mapping, referencing
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CM_ARM_PCI_INTERRUPT_MAP_INFO structures.
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Example:
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(Pci0)
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CM_ARM_PCI_CONFIG_SPACE_INFO
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+----------------------------------------
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v v
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CM_ARM_OBJ_REF CM_ARM_OBJ_REF
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(List of references to (List of references to
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address mappings) interrupt mappings)
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v v
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CM_ARM_PCI_ADDRESS_MAP_INFO[0..N] CM_ARM_PCI_INTERRUPT_MAP_INFO[0..M]
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(A list of address mappings) (A list of interrupt mappings)
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The CM_ARM_PCI_INTERRUPT_MAP_INFO objects cannot be handled individually.
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Device's Pci legacy interrupts that are mapped to the same CPU interrupt
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are grouped under a Link device.
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For instance, the following mapping:
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- [INTA of device 0] mapped on [GIC irq 168]
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- [INTB of device 1] mapped on [GIC irq 168]
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will be represented in an SSDT table as:
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- [INTA of device 0] mapped on [Link device A]
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- [INTB of device 1] mapped on [Link device A]
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- [Link device A] mapped on [GIC irq 168]
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Counting the number of Cpu interrupts used and grouping them in Link
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devices is done through this IRQ_TABLE.
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ASL code:
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Scope (_SB) {
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Device (LNKA) {
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[...]
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Name (_PRS, ResourceTemplate () {
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Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive) { 168 }
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})
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}
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Device (PCI0) {
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Name (_PRT, Package () {
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Package (0x0FFFF, 0, LNKA, 0) // INTA of device 0 <-> LNKA
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Package (0x1FFFF, 1, LNKA, 0) // INTB of device 1 <-> LNKA
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})
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}
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}
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*/
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MAPPING_TABLE IrqTable;
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/// Table to map: Index <-> Pci device
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MAPPING_TABLE DeviceTable;
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} ACPI_PCI_GENERATOR;
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#pragma pack()
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#endif // SSDT_PCIE_GENERATOR_H_
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