79e67b2967
If PcdDxeNxMemoryProtectionPolicy is set to enable protection for memory
of EfiBootServicesCode, EfiConventionalMemory, the BIOS will hang at a page
fault exception triggered by PiSmmCpuDxeSmm.
The root cause is that PiSmmCpuDxeSmm will access default SMM RAM starting
at 0x30000 which is marked as non-executable, but NX feature was not
enabled during SMM initialization. Accessing memory which has invalid
attributes set will cause page fault exception. This patch fixes it by
checking NX capability in cpuid and enable NXE in EFER MSR if it's
available.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
(cherry picked from commit d4d87596c1)
106 lines
3.0 KiB
NASM
106 lines
3.0 KiB
NASM
;------------------------------------------------------------------------------ ;
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; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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; Module Name:
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;
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; SmmInit.nasm
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;
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; Abstract:
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;
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; Functions for relocating SMBASE's for all processors
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;
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;-------------------------------------------------------------------------------
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extern ASM_PFX(SmmInitHandler)
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extern ASM_PFX(mRebasedFlag)
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extern ASM_PFX(mSmmRelocationOriginalAddress)
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global ASM_PFX(gSmmCr3)
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global ASM_PFX(gSmmCr4)
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global ASM_PFX(gSmmCr0)
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global ASM_PFX(gSmmJmpAddr)
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global ASM_PFX(gSmmInitStack)
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global ASM_PFX(gcSmiInitGdtr)
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global ASM_PFX(gcSmmInitSize)
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global ASM_PFX(gcSmmInitTemplate)
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%define PROTECT_MODE_CS 0x8
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%define PROTECT_MODE_DS 0x20
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SECTION .text
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ASM_PFX(gcSmiInitGdtr):
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DW 0
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DQ 0
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global ASM_PFX(SmmStartup)
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ASM_PFX(SmmStartup):
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DB 0x66
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mov eax, 0x80000001 ; read capability
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cpuid
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DB 0x66
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mov ebx, edx ; rdmsr will change edx. keep it in ebx.
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DB 0x66, 0xb8
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ASM_PFX(gSmmCr3): DD 0
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mov cr3, eax
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DB 0x67, 0x66
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lgdt [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
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DB 0x66, 0xb8
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ASM_PFX(gSmmCr4): DD 0
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mov cr4, eax
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DB 0x66
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mov ecx, 0xc0000080 ; IA32_EFER MSR
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rdmsr
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DB 0x66
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test ebx, BIT20 ; check NXE capability
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jz .1
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or ah, BIT3 ; set NXE bit
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wrmsr
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.1:
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DB 0x66, 0xb8
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ASM_PFX(gSmmCr0): DD 0
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DB 0xbf, PROTECT_MODE_DS, 0 ; mov di, PROTECT_MODE_DS
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mov cr0, eax
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DB 0x66, 0xea ; jmp far [ptr48]
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ASM_PFX(gSmmJmpAddr):
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DD @32bit
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DW PROTECT_MODE_CS
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@32bit:
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mov ds, edi
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mov es, edi
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mov fs, edi
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mov gs, edi
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mov ss, edi
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DB 0xbc ; mov esp, imm32
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ASM_PFX(gSmmInitStack): DD 0
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call ASM_PFX(SmmInitHandler)
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rsm
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BITS 16
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ASM_PFX(gcSmmInitTemplate):
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mov ebp, ASM_PFX(SmmStartup)
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sub ebp, 0x30000
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jmp ebp
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ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)
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BITS 32
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global ASM_PFX(SmmRelocationSemaphoreComplete)
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ASM_PFX(SmmRelocationSemaphoreComplete):
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push eax
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mov eax, [ASM_PFX(mRebasedFlag)]
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mov byte [eax], 1
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pop eax
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jmp [ASM_PFX(mSmmRelocationOriginalAddress)]
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global ASM_PFX(PiSmmCpuSmmInitFixupAddress)
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ASM_PFX(PiSmmCpuSmmInitFixupAddress):
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ret
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