7b8fe63561
The comments in the code should speak for themselves; here we note only
two facts:
- The PCI config space writes (to the PCIEXBAR register) are performed
using the 0xCF8 / 0xCFC IO ports, by virtue of PciLib being resolved to
BasePciLibCf8. (This library resolution will permanently remain in place
for the PEI phase.)
- Since PCIEXBAR counts as a chipset register, it is the responsibility of
the firmware to reprogram it at S3 resume. Therefore
PciExBarInitialization() is called regardless of the boot path. (Marcel
recently posted patches for SeaBIOS that implement this.)
This patch suffices to enable PCIEXBAR (and the dependent ACPI table
generation in QEMU), for the sake of "PCIeHotplug" in the Linux guest:
ACPI: MCFG 0x000000007E17F000 00003C
(v01 BOCHS BXPCMCFG 00000001 BXPC 00000001)
PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0x80000000-0x8fffffff]
(base 0x80000000)
PCI: MMCONFIG at [mem 0x80000000-0x8fffffff] reserved in E820
acpi PNP0A08:00: _OSC: OS supports
[ExtendedConfig ASPM ClockPM Segments MSI]
acpi PNP0A08:00: _OSC: OS now controls
[PCIeHotplug PME AER PCIeCapability]
In the following patches, we'll equip the core PCI host bridge / root
bridge driver and the rest of DXE as well to utilize ECAM on Q35.
Cc: Gabriel Somlo <somlo@cmu.edu>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Marcel Apfelbaum <marcel@redhat.com>
Cc: Micha³ Zegan <webczat_200@poczta.onet.pl>
Ref: https://github.com/tianocore/edk2/issues/32
Ref: http://thread.gmane.org/gmane.comp.bios.coreboot.seabios/10548
Suggested-by: Marcel Apfelbaum <marcel@redhat.com>
Reported-by: Micha³ Zegan <webczat_200@poczta.onet.pl>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Tested-by: Gabriel Somlo <somlo@cmu.edu>
Tested-by: Micha³ Zegan <webczat_200@poczta.onet.pl>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
109 lines
3.5 KiB
INI
109 lines
3.5 KiB
INI
## @file
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# Platform PEI driver
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#
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# This module provides platform specific function to detect boot mode.
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# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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##
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = PlatformPei
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FILE_GUID = 222c386d-5abc-4fb4-b124-fbb82488acf4
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MODULE_TYPE = PEIM
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VERSION_STRING = 1.0
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ENTRY_POINT = InitializePlatform
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#
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# The following information is for reference only and not required by the build tools.
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#
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# VALID_ARCHITECTURES = IA32 X64 IPF EBC
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#
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[Sources]
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Cmos.c
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Fv.c
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MemDetect.c
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Platform.c
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Xen.c
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[Packages]
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IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
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MdePkg/MdePkg.dec
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MdeModulePkg/MdeModulePkg.dec
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UefiCpuPkg/UefiCpuPkg.dec
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OvmfPkg/OvmfPkg.dec
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[Guids]
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gEfiMemoryTypeInformationGuid
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gEfiXenInfoGuid
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[LibraryClasses]
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BaseLib
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DebugLib
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HobLib
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IoLib
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PciLib
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PeiResourcePublicationLib
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PeiServicesLib
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PeiServicesTablePointerLib
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PeimEntryPoint
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QemuFwCfgLib
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MtrrLib
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PcdLib
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[Pcd]
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize
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gUefiOvmfPkgTokenSpaceGuid.PcdAcpiPmBaseAddress
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gUefiOvmfPkgTokenSpaceGuid.PcdS3AcpiReservedMemoryBase
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize
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gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId
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gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase
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gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize
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gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base
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gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd
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gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes
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gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize
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gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress
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gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize
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gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
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gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
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gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved
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gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration
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gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode
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gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable
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gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack
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gEfiMdeModulePkgTokenSpaceGuid.PcdPropertiesTableEnable
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gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress
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[FixedPcd]
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gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
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[FeaturePcd]
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gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire
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[Ppis]
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gEfiPeiMasterBootModePpiGuid
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[Depex]
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TRUE
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