7cb96c47a9
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3108 To help mitigate against ROP attacks, add some checks to validate the encryption bit position that is reported by the hypervisor. The first check is to ensure that the hypervisor reports a bit position above bit 31. After extracting the encryption bit position from the CPUID information, the code checks that the value is above 31. If the value is not above 31, then the bit position is not valid, so the code enters a HLT loop. The second check is specific to SEV-ES guests and is a two step process. The first step will obtain random data using RDRAND and store that data to memory before paging is enabled. When paging is not enabled, all writes to memory are encrypted. The random data is maintained in registers, which are protected. The second step is that, after enabling paging, the random data in memory is compared to the register contents. If they don't match, then the reported bit position is not valid, so the code enters a HLT loop. The third check is after switching to 64-bit long mode. Use the fact that instruction fetches are automatically decrypted, while a memory fetch is decrypted only if the encryption bit is set in the page table. By comparing the bytes of an instruction fetch against a memory read of that same instruction, the encryption bit position can be validated. If the compare is not equal, then SEV/SEV-ES is active but the reported bit position is not valid, so the code enters a HLT loop. To keep the changes local to the OvmfPkg, an OvmfPkg version of the Flat32ToFlat64.asm file has been created based on the UefiCpuPkg file UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm. Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <cb9c5ab23ab02096cd964ed64115046cc706ce67.1610045305.git.thomas.lendacky@amd.com>
92 lines
3.0 KiB
Plaintext
92 lines
3.0 KiB
Plaintext
;------------------------------------------------------------------------------
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; @file
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; This file includes all other code files to assemble the reset vector code
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;
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; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2020, Advanced Micro Devices, Inc. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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;
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; If neither ARCH_IA32 nor ARCH_X64 are defined, then try to include
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; Base.h to use the C pre-processor to determine the architecture.
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;
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%ifndef ARCH_IA32
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%ifndef ARCH_X64
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#include <Base.h>
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#if defined (MDE_CPU_IA32)
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%define ARCH_IA32
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#elif defined (MDE_CPU_X64)
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%define ARCH_X64
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#endif
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%endif
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%endif
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%ifdef ARCH_IA32
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%ifdef ARCH_X64
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%error "Only one of ARCH_IA32 or ARCH_X64 can be defined."
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%endif
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%elifdef ARCH_X64
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%else
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%error "Either ARCH_IA32 or ARCH_X64 must be defined."
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%endif
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%include "CommonMacros.inc"
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%include "PostCodes.inc"
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%ifdef DEBUG_PORT80
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%include "Port80Debug.asm"
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%elifdef DEBUG_SERIAL
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%include "SerialDebug.asm"
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%else
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%include "DebugDisabled.asm"
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%endif
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%include "Ia32/SearchForBfvBase.asm"
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%include "Ia32/SearchForSecEntry.asm"
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%ifdef ARCH_X64
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#include <AutoGen.h>
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%if (FixedPcdGet32 (PcdOvmfSecPageTablesSize) != 0x6000)
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%error "This implementation inherently depends on PcdOvmfSecPageTablesSize"
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%endif
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%if (FixedPcdGet32 (PcdOvmfSecGhcbPageTableSize) != 0x1000)
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%error "This implementation inherently depends on PcdOvmfSecGhcbPageTableSize"
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%endif
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%if (FixedPcdGet32 (PcdOvmfSecGhcbSize) != 0x2000)
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%error "This implementation inherently depends on PcdOvmfSecGhcbSize"
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%endif
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%if ((FixedPcdGet32 (PcdOvmfSecGhcbBase) >> 21) != \
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((FixedPcdGet32 (PcdOvmfSecGhcbBase) + FixedPcdGet32 (PcdOvmfSecGhcbSize) - 1) >> 21))
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%error "This implementation inherently depends on PcdOvmfSecGhcbBase not straddling a 2MB boundary"
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%endif
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%define PT_ADDR(Offset) (FixedPcdGet32 (PcdOvmfSecPageTablesBase) + (Offset))
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%define GHCB_PT_ADDR (FixedPcdGet32 (PcdOvmfSecGhcbPageTableBase))
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%define GHCB_BASE (FixedPcdGet32 (PcdOvmfSecGhcbBase))
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%define GHCB_SIZE (FixedPcdGet32 (PcdOvmfSecGhcbSize))
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%define SEV_ES_WORK_AREA (FixedPcdGet32 (PcdSevEsWorkAreaBase))
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%define SEV_ES_WORK_AREA_RDRAND (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 8)
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%define SEV_ES_VC_TOP_OF_STACK (FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) + FixedPcdGet32 (PcdOvmfSecPeiTempRamSize))
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%include "Ia32/Flat32ToFlat64.asm"
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%include "Ia32/PageTables64.asm"
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%endif
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%include "Ia16/Real16ToFlat32.asm"
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%include "Ia16/Init16.asm"
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%include "Main.asm"
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%define SEV_ES_AP_RESET_IP FixedPcdGet32 (PcdSevEsWorkAreaBase)
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%define SEV_LAUNCH_SECRET_BASE FixedPcdGet32 (PcdSevLaunchSecretBase)
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%define SEV_LAUNCH_SECRET_SIZE FixedPcdGet32 (PcdSevLaunchSecretSize)
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%include "Ia16/ResetVectorVtf0.asm"
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