3cbfba02fe
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
99 lines
3.7 KiB
C
99 lines
3.7 KiB
C
/**
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Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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@file
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PchRegsUsb.h
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@brief
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Register names for PCH USB devices.
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Conventions:
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- Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values of bits within the registers
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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- In general, PCH registers are denoted by "_PCH_" in register names
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- Registers / bits that are different between PCH generations are denoted by
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"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
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- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
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at the end of the register/bit names
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- Registers / bits of new devices introduced in a PCH generation will be just named
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as "_PCH_" without <generation_name> inserted.
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**/
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#ifndef _PCH_REGS_USB_H_
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#define _PCH_REGS_USB_H_
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///
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/// USB Definitions
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///
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typedef enum {
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PchEhci1 = 0,
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PchEhciControllerMax
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} PCH_USB20_CONTROLLER_TYPE;
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#define PCH_USB_MAX_PHYSICAL_PORTS 4 /// Max Physical Connector EHCI + XHCI, not counting virtual ports like USB-R.
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#define PCH_EHCI_MAX_PORTS 4 /// Counting ports behind RMHs 8 from EHCI-1 and 6 from EHCI-2, not counting EHCI USB-R virtual ports.
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#define PCH_HSIC_MAX_PORTS 2
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#define PCH_XHCI_MAX_USB3_PORTS 1
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#define PCI_DEVICE_NUMBER_PCH_USB 29
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#define PCI_FUNCTION_NUMBER_PCH_EHCI 0
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#define R_PCH_USB_VENDOR_ID 0x00 // Vendor ID
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#define V_PCH_USB_VENDOR_ID V_PCH_INTEL_VENDOR_ID
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#define R_PCH_USB_DEVICE_ID 0x02 // Device ID
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#define V_PCH_USB_DEVICE_ID_0 0x0F34 // EHCI#1
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#define R_PCH_EHCI_SVID 0x2C // USB2 Subsystem Vendor ID
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#define B_PCH_EHCI_SVID 0xFFFF // USB2 Subsystem Vendor ID Mask
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#define R_PCH_EHCI_PWR_CNTL_STS 0x54 // Power Management Control / Status
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#define B_PCH_EHCI_PWR_CNTL_STS_PME_STS BIT15 // PME Status
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#define B_PCH_EHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13) // Data Scale
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#define B_PCH_EHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9) // Data Select
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#define B_PCH_EHCI_PWR_CNTL_STS_PME_EN BIT8 // Power Enable
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#define B_PCH_EHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0) // Power State
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#define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D0 0 // D0 State
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#define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0) // D3 Hot State
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///
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/// USB3 (XHCI) related definitions
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///
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#define PCI_DEVICE_NUMBER_PCH_XHCI 20
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#define PCI_FUNCTION_NUMBER_PCH_XHCI 0
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//
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/////
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///// XHCI PCI Config Space registers
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/////
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#define R_PCH_XHCI_SVID 0x2C
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#define B_PCH_XHCI_SVID 0xFFFF
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#define R_PCH_XHCI_PWR_CNTL_STS 0x74
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#define B_PCH_XHCI_PWR_CNTL_STS_PME_STS BIT15
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#define B_PCH_XHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13)
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#define B_PCH_XHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9)
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#define B_PCH_XHCI_PWR_CNTL_STS_PME_EN BIT8
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#define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0)
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#define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0)
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#endif
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